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HDLCon 2001 Technical Program
| Thursday, March 1 • 11:45pm - 12:30pm | |
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Discontinuities in Design -- Where's the Next Revolution?
Keynote Speaker• Walden C. Rhines, Chairman and CEO, Mentor Graphics Corp. Abstract: For the last fifteen years, transition to HDL-based ASIC design, with a wide variety of new analysis, verification and creation capabilities, has been the primary driver of change in design methodology. The next major wave of design methodology change will come from developing equivalent design capabilities for FPGA-based system-on-chip platforms. Dr. Rhines will address the capabilities that must be addressed, likely solutions and open questions, as we move to the next major generation of HDL-based design. Biography: Walden C. Rhines, 54, is Chairman and Chief Executive Officer of Mentor Graphics, a leader in worldwide electronic design automation with revenue of $590 million in 2000 Prior to joining Mentor Graphics, Rhines was Executive Vice President in charge of Texas Instruments’ Semiconductor Group with responsibility for over $5 billion of revenue and over 30,000 people. Dr. Rhines holds a bachelor of science degree in metallurgical engineering from the University of Michigan, a master of science and Ph.D. in materials science and engineering from Stanford University, a master of business administration from Southern Methodist University and an Honorary Doctor of Technology degree from Nottingham Trent University. |
| Friday, March 2 • 12:00pm - 2:00pm | |
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Keynote Luncheon Panel • Design and Verification Languages: Are We Heading In The Right Direction?
Moderator: John Cooley - ESNUG This is a busy season for developments in hardware design languages. Our current HDLs are evolving, such as with the new Verilog-2000 standard. At the same time new languages are appearing, such as SuperLog and VERA. Other companies are promoting the use of general purpose languages such as C and Java for hardware design and verification. Do we really need something different than Verilog and VHDL, or are we just finding solutions to problems we don't even have? This panel will explore the various language options available for the design and verification of ASICs, FPGAs and SOCs. Panel members will discuss the viability of these languages for different types of design work. Current language standardization efforts will also be discussed. |
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| Panelists:
Bernd Braune - Get2Chip |
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