Session 2 • Design Techniques and Experiences Using HDLs
	Chair: Janick Bergeron - Qualis Design Corporation		Room: Salons 1-3
Thursday March 1 • 8:30am - 9:45am		Thursday March 1 • 10:15am - 11:05am
2.1	A Comparison of Implementing a Convolutional Error-Correcting Coder-Decoder as an ASIC and an FPGA Azaleah Amina P. Chio, Michelle Marga C. Tabangcura - Advanced Science and Technology Institute	2.4	Simplified Development of Tools for Processing HDLs: Casting Perls before Yaccs Oscar Strohacker, Carl Ashley - IBM Microelectronics
2.2	One Hour Design of a 20+ Bit Decimator of Oversampling Delta-Sigma Converter Using VHDL Przemyslaw Dabrowski - Warsaw University of Technology	2.5	Measuring an Asynchronous Processor's Power and Noise John McCardle, David Chester - Theseus Logic.
2.3	Using GNU Make to Automate Compiles of Mixed-Language SoC Designs Michael D. McKinney - Texas Instruments, Inc.