Session 5 • Modeling and Verification Techniques Using C and C++
	Chair: Kurt Schwartz - Willamette HDL, Inc.		Room: Salon C
Friday March 2 • 8:30am - 9:45am		Friday March 2 • 10:15am - 11:30am
5.1	PCI Device Compliance Testing Using a Mixed C/Verilog Environment Dave Duxstad - Duxstad Consulting Chris Browy - Avery Design Systems	5.4	A Comparison of Sequential VHDL and C, Revised Andreas Zinn, Wolfgang Ecker, Matthias Bauer - Infineon Technologies AG Ernst Bernard - Siemens AG
5.2	System-Level Design Using SuperLog Sunwoo Kim - University of California	5.5	Writing Verilog is Not Much Different than Writing C++ or Java Karl W. Pfalzer -Adaptive Silicon
5.3	Modeling with SystemC: A Case Study J. R. Armstrong - Virginia Tech./Motorola Yuval Ronen - Motorola	5.6	C++ Design, Verification and Automatic Conversion to Synthesizable Verilog on a Large Processor Dan Joyce, Rob Stets, Andreas Nowatzyk - Compaq Computers Inc.