The International HDL Conference and Exhibition

HDLCon 2001 Technical Program

Thursday Sessions Friday Sessions Tutorials Keynote Addresses

Tutorial 2 • Verilog HDL: An Introduction to Modeling ASICs and FPGAs for Simulation and Synthesis
Michael D. Ciletti - University of Colorado

Wednesday February 28 • 8:30am - 12:00 Noon

Designed for prospective users of the Verilog hardware description language, this popular tutorial will introduce its main features, and new features included in Verilog 2000. Several examples of combinational and sequential circuits will be used to illustrate fundamental concepts and key features of the language. Examples will be given to illustrate descriptive styles suitable for synthesis. The objectives of this tutorial are threefold: (1) to introduce never-before users of Verilog to the robust features of the language, (2) to acquaint a broader design community with the features of Verilog-2000, and (3) to introduce the attendees to descriptive styles that are most suitable for synthesis.

	Tutorial 2 • Verilog HDL: An Introduction to Modeling ASICs and FPGAs for Simulation and Synthesis Michael D. Ciletti - University of Colorado
Wednesday February 28 • 8:30am - 12:00 Noon
	Designed for prospective users of the Verilog hardware description language, this popular tutorial will introduce its main features, and new features included in Verilog 2000. Several examples of combinational and sequential circuits will be used to illustrate fundamental concepts and key features of the language. Examples will be given to illustrate descriptive styles suitable for synthesis. The objectives of this tutorial are threefold: (1) to introduce never-before users of Verilog to the robust features of the language, (2) to acquaint a broader design community with the features of Verilog-2000, and (3) to introduce the attendees to descriptive styles that are most suitable for synthesis.