The International HDL Conference and Exhibition

HDLCon 2001 Technical Program

Thursday Sessions Friday Sessions Tutorials Keynote Addresses

Tutorial 5 • VHDL Coding Styles for Hardware Design
Jim Lewis - SynthWorks Design Inc.

Wednesday February 28 • 1:00pm - 4:30pm

This tutorial is a fast paced overview of VHDL design, coding styles and issues relevant to efficient synthesis of ASICs and FPGAs. Different coding styles are analyzed with the objective of achieving a vendor independent, portable synthesis coding style. Detailed do's and don'ts are discussed. Lecture materials illustrate the optimization differences achieved by different VHDL coding styles. Synthesis coding styles recommended in this course are compatible with IEEE standard 1076.6, Standard For VHDL Register Transfer Level Synthesis. As a result, no matter whose synthesis tool you use, the synthesis coding styles and techniques you learn will yield effective results. The detailed lecture guide provides an excellent after-class reference. In addition, students will be provided with VHDL Language and Types Quick Reference Cards. PREREQUISITES: students should be familiar with VHDL and have written some VHDL code.

	Tutorial 5 • VHDL Coding Styles for Hardware Design Jim Lewis - SynthWorks Design Inc.
Wednesday February 28 • 1:00pm - 4:30pm
	This tutorial is a fast paced overview of VHDL design, coding styles and issues relevant to efficient synthesis of ASICs and FPGAs. Different coding styles are analyzed with the objective of achieving a vendor independent, portable synthesis coding style. Detailed do's and don'ts are discussed. Lecture materials illustrate the optimization differences achieved by different VHDL coding styles. Synthesis coding styles recommended in this course are compatible with IEEE standard 1076.6, Standard For VHDL Register Transfer Level Synthesis. As a result, no matter whose synthesis tool you use, the synthesis coding styles and techniques you learn will yield effective results. The detailed lecture guide provides an excellent after-class reference. In addition, students will be provided with VHDL Language and Types Quick Reference Cards. PREREQUISITES: students should be familiar with VHDL and have written some VHDL code.