- Aldec will be presenting a sneak preview of Active-HDL 6.1, expanding its design entry and verification support to include C and C++ in addition to its standard mixed-HDL support. Active-HDL is the fastest, most comprehensive design entry and verification environment for all FPGA devices, including those containing microprocessors.Aldec will also be demonstrating its Riviera tool, the ultimate verification solution for ASICs and SoCs. Riviera includes an HDL Editor, Code Coverage, Design Profiler, Signal Agent and Waveform Viewer/Editor.
|
