- Find more bugs, faster. @HDL is focused on accelerating functional verification. The @Verifier, @Verifier-DP and @Designer products deliver significant verification productivity improvement for SoC development through: system-level design analysis and debugging, automatic formal model checking, extensive multiple clock domain verification and tight integration with existing Verilog simulation environments. With support of industry standard assertion languages (OVA and PSL Sugar), and tight integration with testbench language debugging for OpenVera, @HDL enables design teams to reap immediate productivity gains in SoC verification.
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