| Panelists representing EDA companies and representing companies that design large systems will present their views on methodologies and design/verification languages. As electronic design and verification complexity increases, project schedules are the inevitable victim. New techniques have emerged that target the verification bottleneck; but, layered onto existing procedures, they can promise only incremental improvements. Point tools such as model checkers, automated test generation tools, and similar new technologies represent discontinuities in verification techniques that need a corresponding new methodology to gain maximum advantage from their use. But, what components must be in place to build such a methodology? A single language and unified platform that ties verification tools together, minimizes the inefficient rewriting of tests, and builds off of an existing foundation of models and code would appear to be a natural requirement for a complete verification methodology. This panel of industry experts will explore the requirements for building an effective verification methodology using a single language and unified platform. It will also look at the need for a cohesive hardware design and verification language to bind such a methodology together. What form should this language take? What productivity benefits can be expected from the use of a cohesive methodology and language? |
