| In recent years, a freely downloadable set of Verilog assertions, known as the Open Verification Library (OVL) has sparked interest in a new way of increasing verification efficiency of large Verilog designs. Assertions from the OVL library offer design engineers the ability to add "claims of fact" about their designs. A design engineer can "assert", or claim, that the states in an FSM are encoded onehot, that a bus request should always be acknowledged within three clock cycles, or that certain signal combinations should never occur. With minimal effort, designers and verification engineers can add thousands of checks to a design to efficiently help debug a device under test.
Verilog HDL is evolving to standardize and incorporate assertion capability into the language. Some assertion capability has been added to the Accellera SystemVerilog Standard and assertions are being considered for inclusion in the next IEEE Standard of Verilog. The questions that will be posed to the expert panelists are: Should assertions be part of the next mainstream IEEE Verilog Standard? Should assertions be developed as a separate IEEE1364.2 Standard? Or, should assertions be the domain of third party tools and languages? And why? What assertion standardization and strategy makes the most sense for design and verification engineers?
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