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Speakers/Presenters
Tuesday, February 25, 2003
1:30 PM - 5:00 PM
Session 6 - Real Life Experiences with HDLs and HVLs
6.1 Avoiding Another Verilog/VHDL War: Good Coding Practices for Soft IP Vendors
Dhanendra Jani, Alain Raynaud - Tensilica, Inc.

6.2 Floating Point for VHDL and Verilog
David Bishop - Eastman Kodak

6.3 Mixed Sign Off: What is it and how do I get it done?
 Josef Derner - Model Technology, a Mentor Graphics Co.
Break • 3:00 PM - 3:30 PM
6.4 Seeing the Forest for the Trees (EDA Aiding an Expert Witness)
Stefen Boyd - Boyd Technology, Inc.

6.5 Hex: A Multi-Threaded Verification Environment for an Arm System-on-Chip
 Jeff Breti - Mint Technology, a Division of LSI Logic

6.6 Jeda, a New Functional Verification Language
Atsushi Kasuya, Eugene Zhang - Jeda Research, Inc.