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| Wednesday, February 26, 2003 |
1:00 PM - 5:00 PM
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| Presenters: Tom Fitzpatrick - Synopsys, Inc. Mark Warren - Synopsys, Inc.
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| This tutorial will review, in detail, the four Smart Verification technologies in VCS: advance testbench automation; assertion driven verification; high performance links to C++; and coverage analysis. In addition, key features of the new Accellera SystemVerilog language standard will be introduced, and show how it enables a powerful new methodology that brings design and verification engineers under one language "umbrella". New design and verification constructs being considered in SystemVerilog 3.1 will be shown, as well as how Synopsys’ VCS™ Smart Verification Platform brings all of these capabilities into a single unified environment to maximize productivity of both design and verification teams. |
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