- Veritools provides Verilog, VHDL and SystemC designers with design analysis and verification tools that significantly reduce design time and R&D costs to design and verify RTL designs. Undertow 9, currently the fastest waveform viewing tool on the market, is combined with a powerful source code debugging window to become Undertow 9 Suite and includes Schematic and State Diagram views of the design at no additional costs. Undertow 9 Suite, now includes the new HDLAnalyzer, a complete RTL synthesizer so users can see a complete synthesized schematic of their RTL design using RTL primitive gates.
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