GENERAL INFORMATION

Nothing stimulates the innovative juices of the engineering community within our industry as the two most overriding emotions - fear and frustration. The fear part comes when it is clear that large SOCs are a necessary consequence of the appetite for ever increasing complex systems using ever decreasing semiconductor geometries. With the cost of semiconductor tooling hitting the roof, system development times reducing, larger IP blocks of suspect origin (from a verification point of view) are being incorporated, and the sheer complexity involved- there is much to fear. The frustration comes into play when current EDA tools driven from higher level language descriptions are applied to help mitigate the fear, and while they do their best, they don't quite have that calming effect that one is seeking when chip-zilla goes to tape-out.

To get an SOC to actually function in silicon requires a new level of verification to reduce the fear of dead chip and relieve the frustration of a disconnect between actual functionality vs. specified functionality. In short - "verify or die" is the clarion call that drives engineers to demand design languages that are capable of built-in assertion type verification as well as embrace embedded software as an integral part of the system solution on silicon. This call leads to the emergence of an "executable specification" that has integrity of function because verification tools can demonstrate expected, and also unexpected results. This is precisely why at the last DAC, the emergence of the importance of verification as a discipline was all the buzz.

One thing that can be said about our industry is that engineers find ways to get things done. They then turn around and use the pain they experience to demand that improvements to languages and tools take place. To that end, DVCon becomes the one venue where engineers get to hear from their peers on how to get things done today, and equally have a strong voice to demand that language standards get defined and standardized quickly so they can be used in practice rather than endlessly discussed. That is why DVCon is such a strong technical paper venue as well as a place where one will find a comprehensive set of the right tutorials to get languages into practical use as fast as possible.

Because new system languages have achieved a level of maturity where engineers can and should get their hands on them to begin applying them in practice, the tutorial is an ideal and cost effective way to introduce the essence of a language and the structure of its use. We have an awesome list of targeted tutorials to do just that.

As in past years, the best of our EDA industry is on hand to exhibit their tools and listen to improvements, requirements and suggestions from the very engineers (yourselves) who experience the fear and frustrations of SOC innovation. The value of this engineering feedback is the very reason that we have so many exhibitors on the DVCon floor.

See you at DVCon!

Sincerely,

Frank Weiler
Gerneral Chair