| Today's chip and system companies are faced with enormous designverification challenges, with 70% or more of the total schedule spent in verification. Even the largest companies, with nearly infinite resources, have demonstrated that throwing CPU cycles and people at the simulation problem still doesn't produce the desired result: shorter, bug free design cycles. Are assertions, faster simulators, and testbench languages the answer or just micro-optimizations of a methodology that is fundamentally flawed? Is there hope for a verification methodology that will really yield a clean design with a predictable verification schedule? The answer to these questions involves thinking differently about how to impact fundamental design quality. Decisions must be made about organizational structure (separate design/verification teams vs. designers who also verify), specifications, reuse, level of abstraction, how to work with EDA and IP vendors, etc. Harry Foster, Jasper Chief Methodologist, will lead a panel sharing perspectives on why it's time to think differently about verification, getting the design bugs fixed closer to the source, what organizational/cultural changes need to take place and the move to greater designer accountability.
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