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| Tuesday, March 2, 2004 |
10:30 AM - 12:30 PM
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| 1.1 Design and Verification of a DSP using VHDL, Verilog, SystemC, and C++ Bill Dittenhofer, Greg Tumbush - Starkey Labs. - Colorado IC Design Ctr., Colorado Springs, CO 1.2 Dynamic Power-Down of Peripherals - Issues and Remedies 1.3 SystemC in an SoC - A Success Story 1.4 Should FPGAs be Designed as if They Were ASICs |
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