Time to focus on results

DVCon 2005 comes at a particularly interesting time in the evolution of design and verification languages. As the preeminent conference in the world on the practical application of languages for design and verification this is the place to be to find out the latest news and hear the most in depth discussion about this critical topic.

The industry has made significant progress in addressing the need for system languages, yet public discussion has increasingly revolved around controversies related to standards-making procedures. Instead of more debate on administrative issues, designers urgently need critical capabilities such as more advanced verification features and more powerful assertions. In reality, an emerging confluence of standards promises to deliver these much-needed capabilities to the design community. Accordingly, the discussion about systems languages should more properly focus on the ability of these standards to deliver results to designers urgently looking for more effective design solutions. In particular, the ability of these languages to work together in a coherent fashion gives the best shot at providing a useful design and verification solution. This will be the theme of DVCon 05.

Although concern about standards ownership and procedures has dominated recent discussion, it is time to bring the discussion back to the substantive merits of the system design language standards. These standards evolved in response to a growing level of design complexity that has eclipsed the capabilities of traditional RTL simulation-based methodologies – and still impedes design progress today. Rather than replace existing languages or methodologies, however, these languages promise to enhance existing development capabilities and help coalesce them into a consistent framework for design and verification.

The combination of SystemVerilog, SystemC and the Property Specification Language (PSL) promises a powerful and flexible foundation for design. Together, these standards address clear needs for emerging software-rich designs with critical capabilities including advanced verification features such as solvers, constrained random testing and more. They bring powerful assertion capabilities that, with PSL, provide a bridge to formal verification and the ability to apply assertions across multiple design languages.

DVCon 05 is the place to hear the latest papers about these languages and to take advantage of the many tutorials offered that provide a cost effective way to gain proficiency in the application of languages and methodologies that are emerging. In addition panels and presentations will give updates on the progress in standardization and implementation of these new languages. As in past years, the best of our EDA industry is on hand to exhibit their tools and listen to improvements, requirements and suggestions from the very engineers (yourselves) who experience the fear and frustrations of SOC innovation. The value of this engineering feedback is the very reason that we have so many exhibitors on the DVCon floor.

See you at DVCon.