| Sub-100 nm design capabilities are bringing about a period of rapid change in design methodology—especially in verification. The most pressing need is for a new approach to deal with the complexity of 100M+ gates. Verification now consumes on the average nearly 70% of ASIC development time and for more advanced system-on-chip (SoCs) is approaching 90%. Existing methodologies are stretched to their limits, creating pressure for new approaches. It’s time to introduce a new verification methodology to match the complexity of modern ASIC design.
Dr. Rhines will explore how verification over the past twenty years has been driven by successive waves of innovations, moving designers up the layers of abstraction. Once again, higher complexity is stimulating another era of innovation in design and verification. New techniques are emerging that will support more effective verification at the multiple levels required for advanced SoC design: at the block, intra-block and system level. These innovations are being reinforced by the emergence of standards, ensuring the long-term viability of the advancements.
Walden C. Rhines is Chairman and Chief Executive Officer of Mentor Graphics. He joined Mentor in 1993 from Texas Instruments (TI) where he was most recently Executive Vice President in charge of TI’s semiconductor business. During twenty-one years at TI, he managed all parts of their semiconductor and computer systems businesses and was responsible for the original development of key products such as TI’s TMS 320 family of digital signal processors and speech synthesis components for Speak ‘N Spell. He is currently Chairman of the Design Automation Consortium, a board member of the Semiconductor Research Corporation, Lewis and Clark College and the University of Michigan National Advisory Council. He received a BSE degree from the University of Michigan, an MS and Ph.D. from Stanford University, an MBA from Southern Methodist University and an Honorary Doctor of Technology degree from Nottingham Trent University.
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