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Wednesday, February 16, 2005
10:30 AM - 12:00 PM • Donner Ballroom
Session 8 - IP Design & Development
8.1 Simplifying Complex IP Design with a Hierarchical Modular, Mixed-Language Approach
Mark Lippett, Ayewin Oung - Ignios Ltd., Oxford, Oxfordshire, UK

8.2 Guidelines for SystemVerilog Assertion IP Development
Eduard Cerny - Synopsys, Inc., Marlborough, MA
Janick Bergeron - Synopsys, Inc., Ottawa, ON, Canada
Manoj Kumar Thottasseri - Synopsys, Inc., Koramangala, Bangalore, India

8.3 Function Verification of Design IP - Trust or Hard Work?
Sean Smith - Denali Software, Inc., Palo Alto, CA