| Assertion-Based Verification (ABV) has been widely promoted in recent years, but ABV technology and methodologies are still relatively new, and most designers and verification engineers today still have many questions about how to apply them most effectively. This tutorial presents a broad but detailed overview of how to use assertion languages such as the Accellera Property Specification Language (PSL) and SystemVerilog Assertions (SVA) to improve and accelerate functional verification flows involving VHDL, Verilog, SystemVerilog, and SystemC. The tutorial starts off with a general overview of assertion-based verification techniques and methods, including a short review of PSL and SVA. The tutorial goes on to describe the use of assertions and assertion languages for error detection and for coverage monitoring, including guidelines for writing efficient and portable assertions, and a taxonomy of common assertion forms. The tutorial finishes with an overview of techniques for building reactive testbenches and a sketch of how assertion languages may ultimately be used for abstract specification of a design. Each section is illustrated with examples in PSL and SVA. Attendees will come away with a detailed understanding of how to adopt assertion-based verification within their own verification flows.
Presenters:
- Victor Berman - Cadence Design Systems, Inc., Chelmsford, MA
Erich Marschner - Cadence Design Systems, Inc., Ellicott City, MD
Lisa Piper - Cadence Design Systems, Inc., Allentown, PA
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