Interest in the use of SystemVerilog for verification is strong. Not surprisingly, many organizations that have lead the evolution in verification by using languages such as e and Vera, are demonstrating interest in moving from proprietary languages to SystemVerilog. This tutorial provides guidance on transitioning to a standards-based verification methodology built on SystemVerilog and will be particularly valuable to those already using proprietary languages. Much of the material in this tutorial is general to using SystemVerilog for verification and will benefit anyone seeking guidance on creating an SystemVerilog-based verification methodology.
The concepts and methods presented will be illustrated through the liberal use of an example design and verification environment.
- Outline
1. Verification Environment Building Blocks
a. Environment Setup
b. Connecting the Verification Environment to the Design
c. Bus Functional Models
d. Bus/Interface Master
e. Random Test Generation
f. Checkers
g. Testcases
2. Scoreboarding
a. General scoreboard structure
b. Transformation functions
c. Comparison logic
3. Functional Coverage
a. Functional coverage points
b. Coverage of design and tests
c. Reactivity
4. Special topics
a. File IO
b. String manipulation
c. Object-oriented methods and reuse
d. Connecting to and driving VHDL models, etc.)
Presenters:
- Stephen Bailey - Mentor Graphics Corp., Longmont, CO
Tom Fitzpatrick - Mentor Graphics Corp., San Jose, CA
Michael Horne - Verifica LLC, Portland, OR
Dave Rich - Mentor Graphics Corp., San Jose, CA
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