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| DVCon is looking at way to greatly reduce the cost for engineers to enroll in the tutorials. In this time of intense budgetary restrictions, DVCon is offering 4 sponsored tutorials included in the full conference registration fee. To reserve your tutorial seat(s), please select one morning and one afternoon tutorial you wish to attend.
The minimal cost for Exhibit-only registrants is $50.00 per sponsored tutorial . Monday Sponsored Tutorial registration includes Coffee Breaks and notes to your selected tutorial(s) |
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| Morning Tutorials |
8:00 AM - 12:00 NOON
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Tutorial 1 - SystemVerilog Assertions: Best Practices for Functional Verification sponsored by:  |
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Presenters:
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Ben Cohen - VhdlCohen Publishing, Palos Verdes Peninsula, CA Alex Fasan - Synopsys, Inc., Mountain View, CA John Girard - Synopsys, Inc., Marlboro, MA Jin Hou - Synopsys, Inc., Hillsboro, OR |
Tutorial 2 - Pragmatic ABV: Effective Assertion-Based Verification sponsored by:  |
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Presenters:
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Victor Berman - Cadence Design Systems, Inc., Chelmsford, MA Erich Marschner - Cadence Design Systems, Inc., Ellicott City, MD Lisa Piper - Cadence Design Systems, Inc., Allentown, PA |
| Afternoon Tutorials |
1:00 PM - 5:00 PM
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Tutorial 3 - Transitioning to SystemVerilog for Verification sponsored by:  |
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Presenters:
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Stephen Bailey - Mentor Graphics Corp., Longmont, CO Tom Fitzpatrick - Mentor Graphics Corp., San Jose, CA Michael Horne - Verifica LLC, Portland, OR Dave Rich - Mentor Graphics Corp., San Jose, CA |
| Tutorial 4 - Transaction Level Modeling with the New OSCI SystemC TLM Standard sponsored by: |
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Presenters:
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John Aynsley - Doulos Ltd., Hampshire, UK Stuart Swan - Cadence Design Systems,Inc., San Jose, CA |
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Exhibits: 4:00 PM - 7:00 PM
Cocktail Reception: 5:00 PM - 7:00 PM |
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