DVCon2005

9:00 10:00	Panel 2 - What’s Next for Design and Verification Methodology
	Break
10:30 12:00	Session 7 - Coverage-Driven Verification	Session 8 - IP Design & Development
	Lunch
1:00 2:00	Panel 3 - Designing Quality In: The BetterDesign Paradigm
2:00 3:30	Session 9 - Assertion-Based Verification II	Session 10 - SystemVerilog in Action
	Break
4:00 5:00	Panel 4 - ESL Leadership: Can The US Catch-Up to Europe and Japan?
	Closing Remarks/Best Paper Awards 5:00 PM - 5:30 PM • Donner Ballroom