Moderator: Richard Goering - EE Times, Santa Cruz, CA

Organizers: Karen Bartleson - Accellera Secretary, Dennis Brophy - Mentor Graphics Corp.

Arguably, power management is today's most critical area of integrated circuit design. Of all the issues facing chip and systems designers, none is more burning that the soaring levels of power flowing through their circuits. Many leading-edge designers believe that power has become the dominant factor in the design of modern electronic systems.

EDA vendors have offered various solutions to power management, each with different formats and methods for describing low power design intent. Likewise, leading chip companies are seeking new ways to manage low power in their newest chip designs, and demand a standard method to express low power design intent throughout the IC design flow.

Has there been actual progress on standards or has controversy clouded the vision of a fast, open standard? How do we ensure that low power verification technology uncovers design issues before synthesis? And is this even possible when verification itself is still the critical bottleneck in the industry? Are customers satisfied with the solution so far? What more needs to be done?

The panelists are experts in the fields of low power design and electronic design standards. They are well-qualified to discuss the subject of low power design challenges. The Moderator, Richard Goering, has a keen interest in the topic and is an experienced panel moderator who poses intriguing and in-depth questions.

Panelists: John Goodenough -  ARM Ltd.
Pankaj Mayor - Cadence Design Systems, Inc.
Thomas Blaesi - ChipVision
Gary Delp - LSI Logic
Dennis Brophy - Mentor Graphics Corp.
Mike Keating - Synopsys, Inc.

Moderator: John Cooley - DeepChip.com & EE Times, Holliston, MA

OK, so in prior years we used to call this "The Bigwigs Panel", but if you view the videos of prior panels, you'll see we spent our time talking about all the troubles the EDA industry ran into that year. Here's this year's list of suspects:

Panelists: Rajeev Madhavan - CEO of Magma
Antun Domic - GM of Implementation, Synopsys
Joe Sawicki - GM of Design-to-Silicon, Mentor Graphics
Ted Vucurevich - CTO of Cadence
Vic Kulkarni - CEO of Sequence Design
Atul Sharan - CEO of Clear Shape
Brett Cline - The SystemC Poster Boy
Gary Smith - Gary Smith EDA

Every year Cooley asks his 25,000 member ESNUG mailing list for edgy questions to ask his panelists. Come watch the suspects squirm under this year's interrogations.

Moderator: Harry Foster - Mentor Graphics Corp., Addison, TX

Verification, like an exotic blender concoction, is a multi-dimensional undertaking. The verification endeavor generally spans multiple levels of abstractions, evolves throughout a project's lifecycle, and depends on multiple tools and processes. In addition, success requires coverage metrics to determine the quality and completeness of the verification process, and serve two primary purposes:
1. Identify where we have been (that is, what functionality or implementation structures have been verified)
2. Identify how far we have to go (that is, where the verification process currently stands in terms of completion)
Yet measuring and analyzing coverage, like verification itself, is a multi-dimensional problem-whose recipe for success requires a skill in the art of managing and merging multiple views of data from multiple heterogeneous tools.
With the emergence of recent standards, such as the IEEE Std-1800 SystemVerilog, many verification teams are starting to integrate advanced coverage-driven verification techniques into their flows. Some teams focus entirely on manually specified functional coverage techniques-whose coverage space provides a mapping back to the project's architectural and micro-architectural specifications. Other teams focus on automatically extracted structural coverage techniques to ensure that the implementation is thoroughly exercised. Still other teams blend the multiple techniques in such a way to identify holes in their coverage model.
This panel offers a unique user's perspective of today's coverage problem. Our distinguished panel of industry sous chefs will examine the problems of coverage data management from various user project perspectives, and debate the best approaches for blending coverage.

Panelists: David Lacey - Hewlett-Packard Co.
Jerry Vauk - Advanced Micro Devices
Prakash Rashinkar - Rambus
Vigyan Singhal - Oski Technology
Peter Lafauci - Mentor Graphics Corp.