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 Thursday, February 22, 2007
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9:00 |
Keynote Address Moshe Gavrielov - Executive VP and GM, Verification Division, Cadence Design Systems, Inc. (Donner Ballroom) |
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10:00 |
Break |
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Donner Ballroom |
Oak/Fir Ballroom |
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10:30 |
Session 1 SystemVerilog for Design |
Session 2 SystemC in Action |
12:00 |
Lunch Panel: The Lowdown on Low-Power Design and Verification - Views from the Experts sponsored by:  (Pine/Cedar Ballroom) |
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1:30 |
Session 3 SystemVerilog Assertions |
Session 4 Physical Layer Verification |
3:00 |
Break |
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3:30
5:00 |
Panel 1 (Oak/Fir Ballroom) |
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Exhibit Hours: 4:00 pm - 7:00 pm |
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5:00 |
Cocktail Reception 5:00 pm - 7:00 pm (Cascade Ballroom) |
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