Tutorial sponsored by:

Organizer: John Aynsley - Doulos Ltd.
Presenters: John Aynsley - Doulos Ltd.
Stuart Swan - Cadence Design Systems, Inc.
Trevor Wieman - Intel Corp.
Ryan Bedwell - Freescale Semiconductor, Inc.

Transaction Level Modeling (TLM) is important for architectural exploration and performance modeling, for building virtual prototypes of hardware platforms for early software development, and for writing testbenches for hardware verification. The first release "TLM1" of the OSCI TLM standard in 2005 provided a standard set of interfaces that permit plug-and-play between transaction-level components at the transport layer, particularly useful for untimed modeling in a verification environment.

The successful adoption of TLM depends on the interoperability of models from multiple sources at multiple abstraction levels. Right now, this means the ability to support models of common on-chip busses at the Programmers View (PV) level, to annotate timing onto those models (PVT), and to support Cycle Accurate (CA) modeling. Addressing the challenges of interoperability at these modeling levels has been the focus of the OSCI TLM Working Group over the past year, and this effort resulted in the first release of "TLM2" for public review in December 2006.

After a brief introduction to SystemC and TLM, this tutorial will present an in-depth discussion of the many technical issues raised and addressed by TLM2, will provide examples showing how TLM2 can be used to write interoperable models at the PV and PVT levels, and will offer guidelines for successful TLM modeling.

Agenda:
- A brief introduction to SystemC and TLM plus the role of TLM today
- A review of the OSCI TLM1 standard and how to take advantage of TLM1 principles in practical modeling situations
- An in-depth presentation of the features and implementation of TLM2
- Presentations from two significant industrial users on the motivations, challenges, priorities and implication of TLM adoption
- A glimpse at the new features of TLM2 for 2007