DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and VERA, as well as general purpose languages such as C and C++. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, and transaction-level system design and verification.

Panels at DVCon include topics that are current, have a high-level of interest, and offer at least a bit of controversy. There is no set length for panels, but proposals for 2013 will explain the focus of the panel, why this focus is important and relevant to DVCon attendees, and potential differing approaches to the issues to be discussed by the panel.

Panel proposals are now being reviewed. Stay tuned for the release of the conference program in December to learn about interesting panel topics which will be presented at DVCon February 25-28, 2013.