TUTORIAL: Increasing Productivity with SystemC in Complex System Design and Verification
After a decade of evolution, IEEE 1666™, aka SystemC™, is widely used for high level system design description and verification. As the system complexity increases, SystemC is becoming an enabler to build platforms for advanced design and verification techniques. Some of these techniques include high level synthesis, virtual platforms for prototyping, and a wide array of debug techniques to locate and isolate hard-to-find bugs. In this tutorial, some of the experienced users and tool developers will share their interdisciplinary use of SystemC in building verification environments that provide early hardware access to software developers.