TUTORIAL: Fast Track Your UVM Debug Productivity with Simulation and Acceleration
Modern class-based verification environments like those built with the Accellera Universal Verification Methodology (UVM) very closely resemble complex software systems. Debugging RTL using a class-based Aspect Oriented Programming (AOP) and/or Object Oriented Programming (OOP) verification environment requires a big mindset change for many users who are accustomed to debugging RTL using traditional waveform and log file analysis methodologies. For example, traditional post-process debug techniques are more difficult in this AOP/OOP world because they lack the interactive features such as forward and backward source code single-stepping, searching for arbitrary values and types, and automated go-to-cause analysis.
To reduce debug turnaround time we will show how class-based, software-like environments are more efficiently debugged using low latency interactive debug techniques; where the user has a much broader range of capabilities at their disposal.
We will also explain how new data access to coverage and assertions in acceleration extend these methods to catch bugs unique to system verification. In short, we will provide design and verification engineers with the latest techniques and tools available in the debug space, including solutions combining the best features of both interactive and post process debug using both simulation and acceleration engines.
What the registrant will learn:
- Advantages of interactive debug over traditional post-process debug
- Preparing UVM environments for hardware acceleration
- Advanced post-process debug techniques improving debug productivity by 40 – 50%
- Unique advantages of class-based aware debug technologies
- Application of debug techniques to both simulation and acceleration engines, including assertions and coverage driven verification