Welcome to the 10th year for DVCon!
The Technical Program Committee members are very excited to bring you this year’s program. These papers and posters were selected from a pool of the highest quality of submissions we have seen over the past few years.
The technical sessions (oral and poster presentations) comprise 13 sessions. What you may not know is how these sessions came together. The sessions are self selecting and are based on the submissions, rather than the other way around. So the TPC itself awaited eagerly to find out which sessions emerged! And it didn’t disappoint us... the sessions reflect what we believe is the pulse of the design verification community today.
So what is on tap this year? Here is a random walk through the sessions. You can of course find the details by going to the voting site.
Recently, we have seen a number of standards being actively adopted by the community. Not surprisingly, a session emerged talking about the deployment of UCIS, a coverage interoperability standard that recently got approved by Accellera. And then there is UVM. The industry is enthusiastically adopting this verification methodology, and the papers generally go much beyond how to adopt it. Instead, the community now is looking for discussion on advanced applications. So much so that we had to devote two sessions on this topic alone!
One popular submission area is real case studies. You get to chat with your peers about problems that you are probably working on actively. We see topics ranging from how to verify memory subsystem to the verification of an image processing CPU. In fact, we needed two sessions dedicated to this as well.
And then there are some of the usual, but always exciting topics. We have one dedicated to the practical application of formal and semi-formal techniques. Another area is the mixed signal/power aware design and verification, where both vendor and end-users discuss their challenges.
Over the past three years, we have been noticing some emerging trends. Verification process and resource management is a popular concern. This is expected, since even the smallest verification teams now employ large amount of compute resources, and the demand for resources (people or compute) always outstrips the supply. Another trend is the area of ESL and TLM concerning design and verification beyond the RTL level.
The generalist in you will be excited about the following two sessions... the one on Verification Techniques and the other called Potpourri. In these, we find topics as wide ranging as new ways to bind your design to the verification environment to the effective interpretation of the X’s in your waveform.
Last, and certainly not the least, I will specifically highlight the poster session. This is the 3rd year in a row we have had this session and it is getting very popular with both the attendees and the presenters. Note that these poster submissions have all been fully reviewed by the committee, and the authors also have to submit an accompanying paper which is again duly reviewed by the committee.
In fact, several presenters shared that they liked the poster sessions’ one-on-one mode of interaction with the audience over the traditional oral presentation format. Given the popularity of this session, this year we are instituting a new award to recognize the quality and hard work put into these posters.
Well, I hope this gives you a good idea of what to expect this year! We look forward to seeing you at the event and please feel free to stop any of us on the floor and share your feedback. And remember to vote for your best paper/poster! And of course, do not forget to check out the tutorials and panels as well!
Hoping to see you soon,
-Ambar Sarkar, Ph.D.
Paradigm Works, Inc.
Technical Program Chair