Effects of Abstraction in Stimulus Generation of Layered Protocols within OVM
Josh Rensch - Lockheed Martin Corp.
Jesse Prusi - Lockheed Martin Corp.
February 25-28, 2013
Doubletree, San Jose
Best Paper Award
Best Paper Award
The DVCon Best Paper award is selected by the attendees of the conference each year and reviewed by the steering committee.
2012 Recipients
1st Place:
| 12.1 | SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes | |
| Speaker: | Erik Seligman - Intel Corp. | |
| Authors: | Laurence Bisht - Intel Corp. Dmitry Korchemny - Intel Corp. Erik Seligman - Intel Corp. | |
2nd Place:
| 12.3 | Better Living Through Better Class-Based SystemVerilog Debug | |
| Speaker: | Rich Edelman - Mentor Graphics Corp. | |
| Authors: | Rich Edelman - Mentor Graphics Corp. Raghu Ardeishar - Mentor Graphics Corp. John Amouroux - Mentor Graphics Corp. | |
Honorable Mentions:
| 4.1 | Yikes! Why is My SystemVerilog Testbench so Slow? | |
| Speaker: | Justin Sprague - Cadence Design Systems, Inc. | |
| Authors: | Frank Kampf - IBM Corp. Justin Sprague - Cadence Design Systems, Inc. Adam Sherer - Cadence Design Systems, Inc. | |
| 4.3 | Keeping Up with Chip - The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient | |
| Speaker: | Stuart Sutherland - Sutherland Hdl, Inc. | |
| Authors: | Stuart Sutherland - Sutherland Hdl, Inc. Tom Fitzpatrick - Mentor Graphics Corp. | |
2011 Recipients
Paper 9.1 - Are Macros in OVM & UVM Evil? – A Cost-Benefit Analysis
Adam Erickson - Mentor Graphics Corp.
Low Power Verification Methodology using UPF
Freddy Bembaron - Texas Instruments, Inc.
Rudra Mukherjee, Amit Srivastava, Sachin Kakkar - Mentor Graphics Corp.
Paper 2.2 - Bridging the Application and Design Gap: Utilization of the GBD Proxy Protocol for Remote Control of an RTL Simulation
Kelly Larson - MediaTek, Inc.
Paper 1.3 - Towards a Practical Design Methodology with SystemVerilog Interfaces and Modports
Jonathan Bromley - Doulos Ltd. Paper 6.2 - FEV's Greatest Bloopers: False Positives in Formal Equivalence
Erik Seligman, Joonyoung Kim - Intel Corp.
Session 9 - Innovative Verification Solutions
Paper 9.1 - Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertions
Mark Litterick - Verilab GmbH
Verification Area
Session 3 - Innovative Verification Solutions
Paper 3.3 - Using MatLab and Simulink in a SystemC Verification Environment
Jean Francois Boland - McGill Univ., Montreal, Quebec, Canada
Claude Thibeault - Ecole de Technologie Superieure. Montreal, Quebec, Canada
Zeljko Zilic - McGill Univ., Montreal, Quebec, Canada
Design Area
Session 10 - SystemVerilog in Action
Paper 10.2 - Using SystemVerilog Now with DPI
Rich Edelman, Doug Warmke - Mentor Graphics Corp., San Jose, CA
VerificationArea
Session 2 - Coverage and Assertion-Based Verification
Paper 2.3 - Coverage-Based DV from Testplan to Tapeout using Random Generation and RTL Assertions
Carey Kloss, Dean Chao - Cisco Systems, San Jose, CA
Design Area
Session 1 - Real World Design
Paper 1.1 - Design and Verification of a DSP using VHDL, Verilog, SystemC, and C++
Greg Tumbush, Bill Dittenhofer - Starkey Labs, Colorado Springs, COtechnical program with sponsored tutorials, technical panels, embedded tutorials, and research sessions, as well as informative (and delicious) sponsored luncheons.