MARCH 2-5, 2015

DoubleTree, San Jose

Conference Sponsor: 

MP Associates, Inc.

TUESDAY March 04, 9:00am - 10:30am | Oak Ballroom



SESSION 1

REGULAR SESSION: Advanced Design and Verification
Chair:
Charles Dawson - Cadence Design Systems, Inc.





1.1Advancing System-Level Verification Using UVM in SystemC
 Speaker: Martin Barnasconi - NXP Semiconductors
 Authors: Martin Barnasconi - NXP Semiconductors
François Pêcheux - Univ. Pierre et Marie Curie
Thilo Vörtler - Fraunhofer IIS
1.2Can My Synthesis Compiler Do That? What ASIC and FPGA Synthesis Compilers Support in the SystemVerilog-2012 Standard
 Speaker: Stuart Sutherland - Sutherland HDL, Inc.
 Authors: Stuart Sutherland - Sutherland HDL, Inc.
Don Mills - Microchip Technology, Inc.
1.3Using SystemVerilog Interfaces and Structs for RTL Design
 Speakers: Tom Symons - Oracle Corp.
Nihar Shah - Oracle Corp.
 Authors: Nihar Shah - Oracle Corp.
Tom Symons - Oracle Corp.