MARCH 2-5, 2015

DoubleTree, San Jose

Conference Sponsor: 

MP Associates, Inc.

TUESDAY March 04, 10:30am - 12:00pm | Gateway Foyer



SESSION 1P

POSTER SESSION: Poster Session
Chair:
Shankar Hemmady - Synopsys, Inc.



1P.1Debugging Communicating Systems: The Blame Game – Blurring the Line Between Performance Analysis and Debug
 Speaker: Rich Edelman - Mentor Graphics Corp.
 Authors: Rich Edelman - Mentor Graphics Corp.
Raghu Ardeishar - Mentor Graphics Corp.
1P.2The Future of Formal Model Checking is NOW! Leveraging Formal Methods for RAPID System On Chip Verification
 Speaker: Ram Narayan - Oracle Labs
 Author: Ram Narayan - Oracle Labs
1P.3Checking Security Path with Cadence Incisive Enterprise Verifier IEV: New Application Development
 Speaker: Jose Barandiaran - Cadence Design Systems, Inc.
 Authors: Julia Dushina - STMicroelectronics
Saumil Shah - Cadence Design Systems, Inc.
Joerg Mueller - Cadence Design Systems, Inc.
Vincent Reynolds - Cadence Design Systems, Inc.
1P.4Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
 Speaker: Matthew Ballance - Mentor Graphics Corp.
 Author: Matthew Ballance - Mentor Graphics Corp.
1P.5Using Test-IP Based Verification Techniques in a UVM Environment
 Speaker: Vidya Bellippady - Microsemi Corp.
 Authors: Vidya Bellippady - Microsemi Corp.
Sundar Haran - Microsemi Corp.
Jay O'Donnell - Mentor Graphics Corp.
1P.6Novel Verification Techniques for ARM A15 Multi-Core Subsystem Using IEEE 1647
 Speaker: Vaibhav Mahimkar - Texas Instruments, Inc.
 Authors: Akshit Dayal - Texas Instruments, Inc.
Van Huynh - Texas Instruments, Inc.
Tomas Huynh - Texas Instruments, Inc.
Erwin Hermanto - Texas Instruments, Inc.
1P.7Resetting Anytime with the Cadence UVM Reset Package
 Speaker: Courtney Schmitt - Analog Devices, Inc.
 Authors: Phu L. Huynh - Cadence Design Systems, Inc.
Stephanie McInnis - Cadence Design Systems, Inc.
Uwe Simm - Cadence Design Systems, Inc.
1P.8Applying Transaction-Level Debug and Analysis Techniques to DUT Simulated Activity Using Data-Mining Techniques
 Speaker: Bindesh Patel - Synopsys, Inc.
 Authors: Leo Chai - NVIDIA Corp.
Jun Zhao - Synopsys, Inc.
Bindesh Patel - Synopsys, Inc.
1P.9Making RAL Jump, an Introspection
 Speaker: Jeremy Ridgeway - LSI Corp.
 Authors: Jeremy Ridgeway - LSI Corp.
Karishma Dhruv - LSI Corp.
Manmohan Singh - LSI Corp.
1P.10Demystifying the UVM Configuration Database
 Speaker: Vanessa Cooper - Verilab, Inc.
 Authors: Vanessa Cooper - Verilab, Inc.
Paul Marriott - Verilab, Inc.
1P.11Verifying Multiple DUV Representations with a Single UVM-e Testbench
 Speaker: Matt Graham - Cadence Design Systems, Inc.
 Author: Matt Graham - Cadence Design Systems, Inc.
1P.12Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology
 Speaker: Gaurav K. Verma - Mentor Graphics Corp.
 Authors: Gaurav K. Verma - Mentor Graphics Corp.
Doug Warmke - Mentor Graphics Corp.
1P.13So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
 Speaker: Andreas Meyer - Mentor Graphics Corp.
 Authors: Andreas Meyer - Mentor Graphics Corp.
Alan Hunter - ARM Ltd.
1P.14UVM SchmooVM – I Want My C Tests!
 Speaker: Rich Edelman - Mentor Graphics Corp.
 Authors: Rich Edelman - Mentor Graphics Corp.
Raghu Ardeishar - Mentor Graphics Corp.
1P.15Verification Mind Games - How to Think Like a Verifier
 Speaker: Jeffrey Montesano - Verilab, Inc.
 Authors: Jeffrey Montesano - Verilab, Inc.
Mark Litterick - Verilab, Inc.
1P.16Easier UVM - Coding Guidelines and Code Generation
 Speaker: John Aynsley - Doulos
 Authors: John Aynsley - Doulos
Christoph Sühnel - Doulos
1P.17VIP Shielding
 Speaker: Jeremy Ridgeway - LSI Corp.
 Authors: Jeremy Ridgeway - LSI Corp.
Karishma Dhruv - LSI Corp.
1P.18Bringing Regression Systems Into the 21st Century
 Speaker: David Crutchfield - Cypress Semiconductor Corp.
 Authors: David Crutchfield - Cypress Semiconductor Corp.
Thomas Ellis - Mentor Graphics Corp.
1P.19Are You Really Confident That You Are Getting the Very Best From Your Verification Resources?
 Speaker: Thom Ellis - Mentor Graphics Corp.
 Authors: Darron K. May - Mentor Graphics Corp.
Fritz Ferstl - Univa Corp.
1P.21Connecting the Dots: Application of Formal Verification for SoC Connectivity
 Speaker: Bin Ju - Cadence Design Systems, Inc.
 Author: Bin Ju - Cadence Design Systems, Inc.
1P.22Generation of Constraint Random Transactions for Verification of Mixed-Signal Blocks
 Speaker: Alexander E. Rath - Infineon Technologies AG
 Authors: Alexander E. Rath - Infineon Technologies AG
Sebastian Simon - Infineon Technologies AG
Volkan Esen - Infineon Technologies AG
Wolfgang Ecker - Infineon Technologies AG
1P.23Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-Signal ASSPs
 Speaker: Frank Yang - Analog Devices, Inc.
 Authors: Frank Yang - Analog Devices, Inc.
Andy Sha - Analog Devices, Inc.
Morton Zhao - Analog Devices, Inc.
Yanping Sha - Cadence Design Systems, Inc.
1P.24Is Your Power Aware Design Really X-Aware?
 Speaker: Jitesh Bansal - Mentor Graphics Pvt. Ltd., India
 Authors: Durgesh Prasad - Mentor Graphics Pvt. Ltd., India
Jitesh Bansal - Mentor Graphics Pvt. Ltd., India
1P.25Architectural Evaluation of a Programmable Accelerator for Baseband, Phy and Video Applications using High Level Synthesis
 Speaker: Andy Fox - Really Useful Software and Hardware Company
 Authors: Andy Fox - Really Useful Software and Hardware Company
Steven D. Anderson - Forte Design Systems
1P.26Equivalence Validation of Analog Behavioral Models
 Speaker: Hardik Parekh - STMicroelectronics
 Authors: Manish K. Karna - STMicroelectronics
Hardik Parekh - STMicroelectronics
Mohit Jain - STMicroelectronics
Atul Pandey - Mentor Graphics Corp.
Sandeep Mittal - Mentor Graphics Corp.