MARCH 2-5, 2015

DoubleTree, San Jose

Conference Sponsor: 

MP Associates, Inc.

WEDNESDAY March 05, 8:30am - 9:45am | Oak Ballroom



PANEL: Is Software the Missing Piece In Verification?
Moderator:
Ed Sperling - Semiconductor Engineering
Organizer:
Liz Massingill - Lee Public Relations

System-level verification has become an endemic problem. Verification budgets are stretched with increasing SoC verification complexity, and teams are looking for ways to improve the productivity of their verification efforts. Vendors such as Breker, Mentor and Vayavya are attempting to automate SoC verification through software-driven verification using a variety of approaches. Is software-driven system-level verification a trend that’s expected to grow or is it just hype?

Panelists from different segments of the semiconductor industry will discuss and debate the presumed need, maturity, scalability, and adoptability of software-driven system-level verification tools, as well as what’s needed to get them to mass usability level. In addition, panelists will discuss current approaches to the verification problem and what place this technology has with respect to current verification methodologies such as UVM.


Panelists:
Tom Anderson - Breker Verification Systems, Inc.
Kenneth Knowlson - Intel Corp.
Steve Chappell - Synopsys, Inc.
Sandeep Pendharkar - Vayavya Labs Pvt., Ltd.
Frank Schirrmeister - Cadence Design Systems, Inc.
Mark Olen - Mentor Graphics Corporation