A tutorial on advanced verification techniques based on the latest VMM release.

INTRODUCTION
With verification complexity increasing for each new design, verification engineers must continuously take advantage of advances in verification methodologies to stay productive.  The VMM methodology first introduced in 2005 and deployed on many successful designs has evolved to meet growing verification requirements.  The latest release of VMM enables higher productivity with SystemC/SystemVerilog TLM2 support, enhanced block-to-system reuse, more ease-of-use features and an enhanced register abstraction layer.

Each speaker will focus on a set of new features in the latest release of the VMM methodology and show how they can be used to solve real-life verification challenges.

LEARNING OBJECTIVES
To help verification engineers get maximum benefit from VMM, this tutorial provides application-oriented information on key VMM features that will boost engineers’ productivity and encourage re-use throughout a project's life-cycle and across projects.

Attendees will be provided with theoretical background, familiarity with extended VMM features, and a selection of real-world examples of best-practice VMM usage, giving them confidence to begin using those features in their own projects.