In order to improve verification productivity, engineers are faced with a classic choice: work harder or work smarter. Working harder means either putting in more hours or determining how to apply the same verification techniques you’ve been using to larger and more complex designs without going insane. Working smarter, on the other hand, involves adopting new techniques and advanced technologies that complement what you’re used to doing, but rely on tools and automation to accomplish the necessary efficiencies.

This tutorial will demonstrate an advanced verification flow, showing how the latest verification technologies can be combined within an efficient methodology to provide a highly effective and productive verification of an SoC design. Beginning with a discussion of verification requirements, we will show how to create a verification plan that involves requirements beyond just random constraints and coverage, and to build a comprehensive verification environment to meet those requirements.

The tutorial will cover the following:
• Tracking requirements from design requirements to initial verification plan to full electronic closure
• Creating and verifying RTL blocks synthesized from C++ models using high level synthesis
• Creating and reusing OVM compatible verification components for block and system-level verification
• Applying automated Formal verification and Clock Domain Crossing verification to automate key block-level verification challenges and increase functional coverage
• Integrating multiple block-level verification IP into a system-level environment
• Generating efficient coverage-driven stimulus
• Debugging processor-based system tests and hardware with an overall 6-10x speedup in the time spent finding a defect.
• Accelerating the OVM transaction-based testbench using hardware emulation
• Managing the process through a metric-driven verification flow providing automation, visibility, control and predictability.