According to the “general” consensus, companies are spending 70% of their total time and effort on verification and the trend is upwards. While IP and re-use has helped constrain total design times, it has, if anything, had a detrimental effect on verification. How do we ensure that we minimize the total amount of time, effort and engineering expense spent in verification, while maximizing the total design quality?  Possible ways out include a greater use of formal verification, migration to ESL, additional use of emulation and physical prototyping, intelligent testbenches etc. While it can be argued that each of these can add to verification productivity, this panel will attempt to decide which emerging techniques provides the best value for your money.