Technical Program

On behalf of the DVCon 2009 Steering and Program committees, we invite you to attend the Design & Verification Conference and Exhibition.

The 2009 DVCon Conference promises to be the best attended one in many years. Issues related to design and verification continue to be at the forefront of the problems that need to be solved in the EDA market. We must, as an industry, deliver breakthrough solutions that will allow EDA customers to produce new designs in a manner that optimizes their profit margins, if we are to be perceived as strategic partners in their business model. Innovation may not be enough; we need invention to put us on pace with the continuing progress in silicon fabrication technology.

The design and verification solutions must address different levels of abstraction concurrently, must deal successfully with hardware/software co-development, and must be multi-lingual because the application areas require the use of different languages like Java, C, Verilog, VHDL, SystemC, and SystemVerilog.

Although we must never forget the lessons we learned in the past, we must not be constrained by the way things have been done in the past. We must look at the present problems with a fresh approach, because the nature of the problems facing today's designers and verification engineers is different from what we have faced before.

The available silicon allows us to deal with applications of unprecedented complexity, while posing new issues like power, packaging, and thermal obstacles that cannot be easily solved through scaling, as we used to do. We must ease the verification burden through better design, a goal not easily reachable with traditional tools. The global enterprise adds complexity to the problem, yet it also provides opportunities for solutions. The goal of the Steering Committee of DVCon 2009 is to provide you with a forum to invent, discuss, and refine design and verification techniques that will expand the impact of EDA on the growth and evolution of the electronic industry.