Tuesday Matrix

Tuesday, February 28:

COLOCATED MEETING: Do We Have What It Takes for Full-SoC Verification?
Pine/Cedar Ballroom • 7:30 - 8:30am






 

Time:
8:00am
 
9:00am
 
10:00am
 
11:00am
 
12:00pm
 
1:00pm
 
2:00pm
 
3:00pm
 
4:00pm
 
5:00pm
 
6:00pm
 
Oak Ballroom
Fir Ballroom
San Jose/Santa Clara
Opening Session • Oak Ballroom
Session 1:
Low-Power Techniques
Poster Session 1/Coffee Break • Gateway Foyer
Session 4:
Verification Benchmarking and Efficiency
Session 5:
Formal Techniques
Session 2:
UVM Techniques
Session 3:
SystemC and Beyond
Session 6:
Mixed-Signal Verification
Sponsored Luncheon: Cadence
Earn Your Degree in the Low-Power Arts and Sciences
Pine/Cedar Ballroom
Industry Leaders Panel: The Resurgence of Chip Design

Reception • Bayshore Ballroom

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Exhibits • Bayshore Ballroom • 3:30-6:30pm