Wednesday Matrix

Wednesday, February 29:
 

Time:
8:00am
 
9:00am
 
10:00am
 
11:00am
 
12:00pm
 
1:00pm
 
2:00pm
 
3:00pm
 
4:00pm
 
5:00pm
 
6:00pm
 
Oak Ballroom
Fir Ballroom
San Jose/Santa Clara
Session 7: Verification and Debugging Tips
Poster Session 2/Coffee Break • Gateway Foyer
Session 10: UVM Stimulus Generation
Session 11: Verification Case Studies
Session 8: Getting to Coverage Closure

 

Session 9: UVM in a Multi-Platform World
Session 12: SystemVerilog Tips and Techniques
Sponsored Luncheon: Synopsys
Industry Leaders Verify with Synopsys
Pine/Cedar Ballroom
Keynote Address: Aart de Geus, Synopsys, Inc.
Systemic Collaboration: Principles for Success in IC Design
Coffee Break • Gateway Foyer
Panel:
Build or Buy: Which is the Best Practice for
Hardware-Assisted Verification?

Reception • Bayshore Ballroom


 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Exhibits • Bayshore Ballroom • 4:30-7:00pm