This program is tentative and subject to change.
| Donner | Oak | Fir | Bayshore Ballroom | |
| 9:00-10:30 | Portable Stimulus
| USF-based FMEDA-driven Functional Safety Verification
| IP-XACT
| |
| 10:30-11:00 | Coffee Break (Gateway Foyer) | |||
| 11:00-12:30 | Portable Stimulus (continued)
| USF-based FMEDA-driven Functional Safety Verification (continued)
| Hierarchical CDC and RDC closure with standard abstract models
| |
| 12:30-1:30 | Sponsored Lunch
| Exhibitor Set Up | ||
| 1:30-3:00 | UVM+SA-EDI
| Streamlining Low-Power Verification: From UPF to Signoff
| Functional Safety
| |
| 3:00-3:30 | Coffee Break (Gateway Foyer) | |||
| 3:30-5:00 | UVM-AMS
| Streamlining Low-Power Verification: From UPF to Signoff (continued)
| SystemC
| |
| Donner | Oak | Fir | Bayshore Ballroom | |
| 8:00 – 8:30 | Opening Session (Oak) | |||
| 8:30 – 9:00 | Coffee Break (Gateway Foyer) | |||
| 9:00 – 11:00 | Technical Session | Technical Session | Technical Session | |
| 11:00 – 12:30 | Poster Session | |||
| 12:30 – 13:30 | Sponsored Lunch
| |||
| 13:30 – 14:30 | Keynote (Oak / Fir) | Exhibit Hall Open | ||
| 14:30 – 15:00 | Coffee Break (Gateway Foyer) | |||
| 15:00-17:00 | Technical Session | Technical Session | Technical Session | |
| 17:00 – 18:00 | TPC Reception – Invitation ONLY | |||
| Donner | Oak | Fir | Bayshore Ballroom | |
| 8:00 – 9:00 | Panel (Oak/Fir) | |||
| 9:00 – 9:30 | Coffee Break (Gateway Foyer) | |||
| 9:30 – 11:00 | Technical Session | Technical Session | Technical Session | |
| 11:00 – 12:00 | Poster Ninja Warrior (Oak) | |||
| 12:00 – 13:30 | Lunch | |||
| 13:30 – 14:30 | Invited Speaker (Oak/Fir) | Exhibit Hall Open | ||
| 14:30-15:00 | Coffee Break (Gateway Foyer) | |||
| 15:00- 16:30 | Technical Session | Technical Session | Technical Session | |
| 16:30 – 17:00 | Coffee Break (Gateway Foyer) | |||
| 17:00 – 17:30 | Best Paper Presentation (Bayshore Ballroom) | |||
| 17:30 – 18:30 | Exhibitor Reception (Bayshore Ballroom) | |||
| Cascade | Donner | Siskiyou | |
| 9:00- 10:30 | Smart Verification: Faster is not enough!
| Emulation Moves Into 4-State Logic and Real Number Modeling
| Your SoC, Your Topology |
| 10:30-11:00 | Coffee Break (Gateway Foyer) | ||
| 11:00-12:30 | Smart Verification: Faster is not enough! (continued)
| FPGA Prototyping for Large Multi-Die / Multi-Core Designs
| Advanced UCIe-based Chiplets verification from IP to SoC
|
| 12:30-1:30 | Sponsored Lunch
| ||
| 1:30-3:00 | Expanding role of Static Signoff in Verification Coverage
| RISC-V Core Verification: A New Normal in Verification Techniques | SystemC Code Generation using Large Language Models
|
