1088. PSS action sequence modeling using Machine Learning
Moonki Jang, Samsung Electronics; Myeongwhan Hyun, Samsung Electronics; Hyunkyu Ahn, Samsung Electronics; Jiwoong Kim, Samsung Electronics; Yunwhan Kim, Samsung Electronics; Dongjoo Kim, Samsung Electronics
1078. Using Portable Stimulus Standard’s Hardware-Software Interface (PSS HSI) to validate 4G/5G Forward Error Correction Encoder/Decoder IP in emulation & silicon
Vinit Shenoy, Intel; Suresh Vasu, Intel; Joydeep Maitra, Intel; Nithin Venkatesh, Intel; Suhas Reddy, Intel; Luis Campos, Intel
1030. Co-Developing IP and SoC Bring-up Firmware with PSS
Matthew Ballance, Siemens Digital Industries Software
1091. A UVM SystemVerilog Testbench for Analog/Mixed-Signal Verification: A Digitally-Programmable Analog Filter Example
Charles Dancak, Betasoft Consulting Inc
1054. Mixed-signal Functional Verification Methodology for embedded Non-volatile Memory using ESP simulation
SangGi Do, Samsung Electronics; Jieun Park, Samsung Electronics; Dohui Kim, Samsung Electronics; Jungkyu Jang, Samsung Electronics
1051. Mixed-Signal Design Verification: Leveraging the Best of AMS and DMS
Rock Shi, Analog Devices; Padmashree Bhinge, Analog Devices; Preston Birdsong, Analog Devices; Geeta Chaitanya, Analog Devices; Kunal Jani, Analog Devices
1005. Modeling Memory Coherency during concurrent/simultaneous accesses
subramoni parameswaran, Xilinx
1007. BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem
Debarshi Chatterjee, Nvidia Corporation; Ismet Bayraktaroglu, Nvidia Corporation; Nikhil Sathe, Nvidia Corporation; Kavya Shagrithaya , Nvidia Corporation; Siddhanth Dhodhi , Nvidia Corporation; Spandan Spandan Kachhadiya , Nvidia Corporation
1017. CAMEL: A Flexible Cache Model for Cache Verification
Yue Liu, Mediatek.inc; Fang Liu, Mediatek.inc; Yunyang Song, Mediatek.inc
1008. Emulation based Power and Performance Workloads on ML NPUs
Pragati Mishra, Arm Ltd; Ritu Suresh, Arm Ltd; Issac Zacharia, Arm Ltd; Jitendra Aggarwal, Arm Ltd
1012. Hybrid Emulation: Accelerating Software driven Verification and Debug
Issac Zacharia, Arm Ltd; Jitendra Aggarwal, Arm Ltd
1040. Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges
Rohit Sinha, Intel; Kavya Kotha, Intel
1042. Modeling Analog Devices using SV-RNM
Mariam Maurice, Siemens EDA (formerly Mentor Graphics)
1045. A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation
Thomas Soong, Intel; Chenhui Huang, Intel; Christopher Browne, Intel
1050. Case Study: Successes and Challenges of Reuse
Mike Chin, Intel; Jonathan Edwards, Intel; Hooi Jing Tan, Intel; Josh Pfrimmer, Intel
1058. Enhanced Dynamic Hybrid Simulation Framework for Hardware-Software Verification
Victor Besyakov, Untether AI
1064. Confidently Sign-off any Low-Power Designs without Consequences
Madhur Bhargava, Siemens EDA; Jitesh Bonshal, Siemens EDA; Progyna Khondkar, Siemens EDA
1067. Successive Refinement – An approach to decouple Front-End and Back-end Power Intent
kavya kotha, Intel Technology Pvt Ltd; Rohit kumar Sinha, Intel Technology Pvt Ltd
1068. Novel GUI Based UVM Test Bench Template Builder
Vignesh Manoharan, Aeva
1073. Accelerating Performance, Power and Functional validation of Computer Vision Use cases on next generation Edge Inferencing Products
Yoga Priya Vadivelu, Intel Technology India Pvt Ltd; Arpan Shah, Intel Technology India Pvt Ltd; Deepinder Singh Mohoora, Intel Technology India Pvt Ltd; Ullas Piyush kanti karmaka, Intel Technology India Pvt Ltd; Praveen Buddireddy, Intel Technology India Pvt Ltd
1082. Pre-Silicon Validation of Production BIOS, Software Use Cases and Accelerator IP Workloads using Hybrid System Level Emulation SoC Platform
Neeraj Gupta, Intel Technology India Pvt Ltd; Reddaiah Yedoti, Intel Technology India Pvt Ltd; Dixit Sethi, Intel Technology India Pvt Ltd; Sarvesh Kumar Pandey, Intel Technology India Pvt Ltd
1085. Avoiding Confounding Configurations: An RDC Methodology for Configurable Designs
Eamonn Quigley, Arm; Jonathan Niven, Arm; Kurt Takara, Siemens; Christopher Giles, Siemens
1090. Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC
Vishal Baskar, Siemens Industry Software Inc – Siemens EDA
1024. Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus
Debarshi Chatterjee, Nvidia Corporation; Spandan Kachhadiya , Nvidia Corporation; Ismet Bayraktaroglu, Nvidia Corporation; Siddhanth Dhodhi , Nvidia Corporation
1037. Two-stage framework for corner case stimuli generation Using Transformer and Reinforcement Learning
Chung-An Wang, MediaTek Inc.; Chiao-Hua Tseng, MediaTek Inc.; Chia-Cheng Tsai, MediaTek Inc.; Tung-Yu Lee, MediaTek Inc.; Yen-Her Chen, MediaTek Inc.; Chien-Hsin Yeh, MediaTek Inc.; Chia-Shun Yeh, MediaTek Inc.; Chin-Tang Lai, MediaTek Inc.
1001. Test Parameter Tuning with Blackbox Optimization: A Simple Yet Effective Way to Improve Coverage
Qijing Huang, UC Berkeley; Hamid Shojaei, Google; Fred Zyda, Google; Azade Nazi, Google; Shobha Vasudevan, Google; Sat Chatterjee, [email protected]; Richard Ho, riho
1020. Adaptive Test Generation for Fast Functional Coverage Closure
Azade Nazi, Google Research; Qijing Huang, UC Berkeley; Hamid Shojaei, Google; Hodjat Asghari Esfeden, Google; Azalia Mirhosseini, Google Research, Brain; Richard Ho, Google
1033. Accelerating Error Handling Verification of Complex Systems: A Formal Approach
Bhushan Parikh, Intel Corporation; Peter Graniello, Intel Corporation; Neha Rajendra, Intel Corporation
1086. How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage
Mark Eslinger, Siemens; Joe Hupcey III, Siemens; Nicolae Tusinschi, Siemens
1060. A Hybrid Verification Solution to RISCV Vector Extension
Chenghuan Li, Mediatek.inc; Yanhua Feng, Mediatek.inc; Liam Li, Mediatek.inc
1018. Innovative Uses of SystemVerilog Bind Statements within Formal Verification
Xiushan Feng, Samsung Austin R&D Center; Christopher Starr, Samsung Austin R&D Center
1003. A New Approach to Easily Resolve the Hidden Timing Dangers of False Path Constraints on Clock Domain Crossings
Yossi Mirsky, Intel; Omri Dassa, Intel
1070. Advanced Functional Verification for Automotive System on a Chip
Jaein Hong, Samsung Electronics; Jieun Jeong, Samsung Electronics; Namyoung Kim, Samsung Electronics; Hongkyu Kim, Samsung Electronics; Sungcheol Park, Samsung Electronics; Sangjun Mun, Cadence Design Systems
1055. Leaping Left: Seamless IP to SoC Hand-off
Swetha Thiagarajan, INTEL; Rashika Madan, INTEL; Hiran Morar, INTEL; Sangeivi Sivagnanasundaram, INTEL
1048. Is it a software bug? It is a hardware bug?
Horace Chan, Microchip; Mame Maria Mbaye, Microchip; Sim Ang, Microchip
1034. Caching Tool Run Results in Large-Scale RTL Development Projects
Ashfaq Khan, Intel Corporation
1041. Finding a Needle in a Haystack: A Novel Log Analysis Method with Test Clustering in Distributed System
Jin Choi, Samsung Electronics Co., Ltd.; Sangwoo Noh, Samsung Electronics Co., Ltd.; Sooncheol Hong, Samsung Electronics Co., Ltd.; Hanna Jang, Samsung Electronics Co., Ltd.; Seonhee Yim, Samsung Electronics Co., Ltd.; Seonil Brian Choi, Samsung Electronics Co., Ltd.
1043. Machine Learning Based Verification Planning Methodology Using Design and Verification Data
Hanna Jang, Samsung; Seonghee Yim, samgsung; Sunchang Choi, samgsung; Seonil Brian Choi, Samgsung
1057. Optimizing Turnaround Times In Continuous Integration Using Scheduler Implementation
Robert Strong, Samsung
1061. Raising the level of Formal Signoff with End-to-End Checking Methodology
Ping Yeung, Oski Technology; Arun Khurana, Oski Technology; Dhruv Gupta, Oski Technology; Ashutosh Prasad, Oski Technology; Achin Mittal, Oski Technology
1099. Hopscotch: A Scalable Flow-Graph Based Approach to Formally Specify and Verify Memory-Tagged Store Execution in Arm CPUs
Vikram Khosa, Arm; Sai Komaravelli, Arm; Madhu Iyer, Arm; Abhinav Sethi, Arm
1011. Never too late with formal: Stepwise guide for applying formal verification in post-silicon phase to avoid re-spins
Anshul Jain, Intel Corporation; Aarti Gupta, Intel Corporation; Achutha KiranKumar V M, Intel Corporation; Bindumadhava Ss, Intel Corporation; Shivakumar S Kolar, Intel Corporation; Siva Gadey NV, Intel Corporation
1032. Maximizing Formal ROI through Accelerated IP Verification Sign-off
Hao Chen, Intel Corporation; Kamakshi Sarat Vallabhapurapu, Intel Corporation; Scott Peverelle, Intel Corporation; Rosanna Yee, Intel Corporation; Hee Chul Kim, Intel Corporation; Johann Te, Intel Corporation; Jacob Hotz, Intel Corporation
1053. Metadata Based Testbench Generation
Daeseo Cha, Samsung Electronics
1013. Automatic Translation of Natural Language to SystemVerilog Assertions
Abhishek Chauhan, Agnisys Technology Pvt. Ltd.
1065. A Comparative Study of CHISEL and SystemVerilog, Based on Logical Equivalent SweRV-EL2 RISC-V Core
Junaid Ahmed, Lampro Mellon; Waleed Bin Ehsan, Lampro Mellon; Laraib Khan, Lampro Mellon; Asad Aleem, Lampro Mellon; Agha Ali Zeb, Lampro Mellon; Sarmad Paracha, Lampro Mellon; Abdul Hameed Akram, Lampro Mellon; Aashir Ahsan, Lampro Mellon
1094. Flattening the UVM Learning Curve: Automated solutions for DSP filter Verification
Avinash Lakshminarayana, Silicon Laboratories, Inc.; Eric Jackowski, Silicon Laboratories, Inc.; Eric Cigan, MathWorks; Mark Lin, MathWorks
1049. Advanced UVM command line processor for central maintenance and randomization of control knobs
Siddharth Krishna Kumar, Samsung Austin Research Center
1004. Fnob: Command Line-Dynamic Random Generator
Haoxiang Hu, Facebook, Inc.; Tuo Wang, Facebook, Inc.
1093. What Does the Sequence Say? Powering Productivity with Polymorphism
Rich Edelman, Siemens EDA
1100. Hierarchical UPF: Uniform UPF across FE & SD
Dipankar Narendra Arya, Intel; Balaji Vishwanath Krishnamurthy, Intel; Aditi Nigam, Intel; Tahir Ali, Intel
1047. Path-based UPF Strategies Optimally Manage Power on your Designs
Progyna Khondkar, Siemens EDA
1029. Problematic Bi-Directional Port Connections: How Well is Your Simulator Filling the UPF LRM Void?
Brandon Skaggs, Cypress Semiconductor, An Infineon Technologies Company
1107. Extension of the power-aware IP reuse approach to ESL
Antonio Genov, NXP
1081. SystemC Virtual Prototype: Ride the earliest train for Time-To-Market !
Shweta Saxena, Analog Devices Inc; Mahantesh Danagouda, Analog Devices Inc
1071. Evaluating the feasibility of a RISC-V core for real-time applications using a virtual prototype
Juan Santana, Fraunhofer IIS/EAS; Gabriel Pachiana, Fraunhofer IIS/EAS; Thomas Markwirth, Fraunhofer IIS/EAS; Christoph Sohrmann, Fraunhofer IIS/EAS; Bernhard Fischer, Siemens AG; Martin Matschnig, Siemens AG
