February 27 - March 2, 2017

DoubleTree Hotel, San Jose, CA

DVCon U.S. Best Paper & Posters

Conference attendees registered with an all access, conference or one-day only registration package,  are the judges for the 2017 Best Paper and Poster Award during the conference.  The 2017 recipients of the 2017 Best Paper and Poster Award will be announced Wednesday, March 1. 

Thank you to our sponsor:

2016 Recipients

Best Paper - 1st Place

8.2 Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 Eldon G. Nelson - Intel Corp.

Best Paper - 2nd Place

5.1 SystemVerilog Interface Classes - More Useful Than You Thought Stan Sokorac - ARM, Inc.

Best Paper - 3rd Place

9.3 Functional Coverage Collection for Analog Circuits – Enabling Seamless Collaboration Between Design and Verification Zhipeng Ye, Honghuang Lin, Asad Khan - Texas Instruments, Inc.

Best Poster - 1st Place

4P.32 Marrying Simulation and Formal Made Easier! Lun Li, Durga Rangarajan, Christopher Starr, James Greene - Samsung Austin R&D Center;
Nitin Mhaske - Synopsys, Inc.

Best Poster - 2nd Place

4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming Krishnan Balakrishnan, Courtney Fricano, Kaushal M. Modi - Analog Devices, Inc.

Best Poster - 3rd Place

4P.14 How Do You Verify Your Verification Components Neil Johnson - XtremeEDA Corp.;
Joshua W. Rensch - Superion Technology

2015 Recipients

Best Paper

10.1 I Created the Verification Gap Ram Narayan, Tom Symons - Oracle LabsDownload

Best Poster

4P.22 Randomizing UVM Config DB Parameters Jeremy Ridgeway - Avago TechnologiesDownload

Paper Honorable Mentions

9.3 Mining Coverage Date for Test Set Coverage Efficiency Monica C. Farkash, Balavinayagam Samynathan -Univ. of Texas at Austin;
Bryan Hickerson, Michael Behm - IBM Corp.
Download
10.2 Lies, Damned Lies, and Coverage Mark Litterick - Verilab, Inc.Download

Poster Honorable Mentions

4P.11 SystemVerilog Constraint Layering via Reusable Randomization Policy Classes John Dickol - Samsung Austin R & D CenterDownload
4P.12 Versatile UVM Scoreboarding Jacob S. Andersen, Peter Jensen, Kevin K. Steffensen - SyoSil ApSDownload
 

2014 Recipients

Best Paper

4.2 Determining Test Quality Through Dynamic Runtime Monitoring of SystemVerilog Assertions Kelly D. Larson - NVIDIA Corp.Download

Best Poster

1P.14 UVM SchmooVM - I Want My C Tests! Rich Edelman, Raghu Ardeishar - Mentor Graphics Corp.Download

Paper Honorable Mentions

2.1 Sign-Off with Bounded Formal Verification Proofs Vigyan Singhal, HarGovind Singh - Oski Technology, Inc.
NamDo Kim, Junhyuk Park - Samsung Electronics Co., Ltd.
Download
5.2 Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks and System Level Verification David C. Brownell, Courtney Schmitt - Analog Devices, Inc.Download

Poster Honorable Mentions

1P.12 Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology Gaurav K. Verma, Doug Warmke - Mentor Graphics Corp.Download
1P.2 The Future of Formal Model Checking is NOW! Leveraging Formal Methods for RAPID System On Chip Verification Ram Narayan - Oracle LabsDownload