February 25-28, 2019

DoubleTree Hotel, San Jose, CA

DVCon U.S. Best Paper & Posters

All Access, Conference Only and One-Day only registrants are entitled to vote for the “DVCon Best Paper and Poster” awards. The attendees are the judges! Place your votes on Tuesday and Wednesday.

Thank you to our Sponsor:

2018 Recipients

Best Paper - 1st Place

7.3 My Testbench Used to Break! Now it Bends: Adapting to Changing Design Configurations Jeffery Vance, Jeffrey Montesano, Kevin Vasconcellos, Kevin Johnston - Verilab, Inc.Download

Best Paper - 2nd Place

12.3 Error Injection in a Subsystem Level Constrained Random UVM Testbench Jeremy Ridgeway, Hoe Nguyen - Broadcom LimitedDownload

Best Paper - 3rd Place

6.1 Deep Predictive Coverage Collection Rajarshi Roy, Chinmay Duvedi, Saad Godil, Mark Williams - NVIDIA Corp.Download

Best Poster - 1st Place

4.18 Is Specman Still Relevant? Using UVM-ML to Take Advantage of Multiple Verification Languages Timothy Pertuit, Doug Gibson, David Lacey - Hewlett Packard EnterpriseDownload

Best Poster - 2nd Place

4.16 Fast Track Formal Verification Signoff Mandar Munishwar - Qualcomm, Inc., Sandeep Jana - Synopsys (India) Pvt. Ltd., Xiaolin Chen, Arunava Saha - Synopsys, Inc.Download

Best Poster - 3rd Place

4.26 Tired of Slow Gate Level Design Verification? Use these Efficient Modelling Styles and Methodology Gabriel Chidolue, Rohit Jain, Shobana Sudhakar - Mentor, A Siemens BusinessDownload

2017 Recipients

Best Paper

7.2 Optimizing Random Test Constraints Using Machine Learning Algorithms Stan Sokorac - ARM, Inc.Download

Best Poster

4P.18 A New Approach for Generating View Generators Johannes Schreiner - Infineon TechnologiesDownload

Paper Honorable Mentions

7.1 Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation Eldon Nelson - Intel Corp.Download
10.1 Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification Honghuang Lin - Texas Instruments, Inc.Download

Poster Honorable Mentions

4P.17 Automatic Debug Down to the Line of Code Daniel Hansson - Verifyter ABDownload
4P.6 End to End Formal Verification Strategies for IP Verification Jacob Maas - Microsoft Corp.Download

2016 Recipients

Best Paper

8.2 Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemsVerilog 1800-2012 Eldon G. Nelson - Intel Corp.Download

Best Poster

4P.32 Marrying Simulation and Formal Made Easier! Lun Li, Durga Rangarajan, Christopher Starr, James Green - Samsung Austin R&D Center; Nitin Mhaske - Synopsys, Inc.

Paper Honorable Mentions

5.1 SystemVerilog Interface Classes - More Useful Than You Thought Stan Sokorac - ARM, Inc.Download
9.3 Functional Coverage Collection for Analog Circuits - Enabling Seamless Collaboration Between Design and Verification Zhipeng Ye, Honghuang Lin, Asad Khan - Texas Insturments, Inc.Download

Poster Honorable Mentions

4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming Krishnan Balakrishnan, Courtney Fricano, Kaushal M. Modi - Analog Devices, Inc.Download
4P.14 How Do You Verify Your Verification Components Neil Johnson - XtremeEDA Corp.; Joshua W. Rensch - Superion TechnologyDownload