DVCon U.S. Best Paper & Posters

DVCon U.S. 2017 attendees were the judges for the 2017 Best Paper and Poster Award; thank you for your participation.

Thank you to our sponsor:

2017 Recipients

Best Paper - 1st Place

7.2 Optimizing Random Test Constraints Using Machine Learning Algorithms Stan Sokorac - ARM, Inc.

Best Paper - 2nd Place

7.1 Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation Eldon Nelson - Intel Corp.

Best Paper - 3rd Place

10.1 Machine Learning based PVT Space Coverage and Worst Case Exploration In Analog and Mixed-Signal Design Verification Honghuang Lin - Texas Instruments, Inc.

Best Poster - 1st Place

4P.18 A New Approach for Generating View Generators Johannes Schreiner - Infineon Technologies

Best Poster - 2nd Place

4P.17 Automatic Debug Down to the Line of Code Daniel Hansson - Verifyter AB

Best Poster - 3rd Place

4P.6 End to End Formal Verification Strategies for IP Verification Jacob Maas - Microsoft Corp.

2016 Recipients

Best Paper

8.2 Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemsVerilog 1800-2012 Eldon G. Nelson - Intel Corp.Download

Best Poster

4P.32 Marrying Simulation and Formal Made Easier! Lun Li, Durga Rangarajan, Christopher Starr, James Green - Samsung Austin R&D Center; Nitin Mhaske - Synopsys, Inc.

Paper Honorable Mentions

5.1 SystemVerilog Interface Classes - More Useful Than You Thought Stan Sokorac - ARM, Inc.Download
9.3 Functional Coverage Collection for Analog Circuits - Enabling Seamless Collaboration Between Design and Verification Zhipeng Ye, Honghuang Lin, Asad Khan - Texas Insturments, Inc.Download

Poster Honorable Mentions

4P.22 Improving the UVM Register Model: Adding Product Feature Based API for Easier Test Programming Krishnan Balakrishnan, Courtney Fricano, Kaushal M. Modi - Analog Devices, Inc.Download
4P.14 How Do You Verify Your Verification Components Neil Johnson - XtremeEDA Corp.; Joshua W. Rensch - Superion TechnologyDownload

2015 Recipients

Best Paper

10.1 I Created the Verification Gap Ram Narayan, Tom Symons - Oracle LabsDownload

Best Poster

4P.22 Randomizing UVM Config DB Parameters Jeremy Ridgeway - Avago TechnologiesDownload

Paper Honorable Mentions

9.3 Mining Coverage Date for Test Set Coverage Efficiency Monica C. Farkash, Balavinayagam Samynathan -Univ. of Texas at Austin;
Bryan Hickerson, Michael Behm - IBM Corp.
10.2 Lies, Damned Lies, and Coverage Mark Litterick - Verilab, Inc.Download

Poster Honorable Mentions

4P.11 SystemVerilog Constraint Layering via Reusable Randomization Policy Classes John Dickol - Samsung Austin R & D CenterDownload
4P.12 Versatile UVM Scoreboarding Jacob S. Andersen, Peter Jensen, Kevin K. Steffensen - SyoSil ApSDownload