February 26 - March 1, 2018

DoubleTree Hotel, San Jose, CA

Call for Extended Abstracts- Deadline Now August 18th

 View Call For Abstracts PDF Extended Abstract Template Submit Now!

 

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.

In addition to the specific topic areas suggested below, submissions may incorporate:

  • usage of Electronic Design Automation (EDA) tools such as simulation, emulation, formal verification, virtual prototyping and/or FPGA prototyping
  • FPGA-based designs
  • usage of specialized design and verification languages such as SystemVerilog, SystemC, and e
  • assertions in SVA or PSL
  • the use of general purpose and scripting languages such as C, C++, Perl, Python, Tcl and others
  • applications of the new Accellera Portable Stimulus Standard
  • applications of design patterns or other innovative language techniques
  • the use of AMS languages
  • Internet of Things applications

This call for abstracts solicits for papers and corresponding presentations that are highly technical and reflect real-life experiences and emerging trends in various domains. Submissions are encouraged in (but not restricted to) the following areas:

Topic Area 1: Verification & Validation

  • Advanced methodologies and testbenches
  • Verification processes, regressions and resource management
  • Debug and analysis of complex designs
  • Multi-language design and verification
  • Hardware/Software co-design and co-verification of embedded systems

Topic Area 2: Safety-Critical Design and Verification

  • Verification and DO-254 compliance
  • Automotive ISO 26262 Design and Verification Challenges
  • Medical or Industrial Verification Challenges
  • Requirements-Driven Verification Methodologies
  • IP protection and security

Topic Area 3: Machine Learning and Big Data

  • Automating the Optimization of Verification Processes
  • Coverage metrics and data analysis
  • Performance modeling and/or analysis

Topic Area 4: Design and Verification Reuse and Automation

  • Bridging verification and validation across multiple engines
  • SoC and IP integration methods and tools
  • Automated stimulus generation methods
  • Configuration management of IP and abstraction levels
  • Interoperability of models and/or tools
  • High-level synthesis from ESL languages
  • Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping

Topic Area 5: Mixed-Signal Design & Verification

  • Mixed-signal design & verification techniques
  • Real-value modeling approaches
  • Application of mixed-signal extensions for UVM

Topic Area 6: Low-Power Design & Verification

  • Low-power design and verification
  • Clock domain crossing verification
  • Power modeling, estimation and management

DVCon honors the Best Paper/Presentation and Best Poster submissions. The awards will be selected by the attendees at DVCon, based on the quality of both the paper and the presentation. So please submit your abstract and join DVCon U.S. 2018!

Please submit your extended abstract - a minimum of 600 words, a maximum of 1200 words (approximately 2 pages, not including diagrams, figures or tables) - by EXTENDED to August 18th to the DVCon.org website outlining your proposed presentation.

Full instructions and details for the extended abstract submission process can be found on DVCon.org.

Extended Abstract Submission Guidelines

The extended abstract should provide enough details so that the Technical Program Committee can evaluate the potential quality of your completed paper and the interest of the DVCon attendees in your presentation. 

An extended abstract is expected to include the following details:

  • Proposed paper title
  • Name, affiliation, phone number, mailing address and email address for all authors.
  • An introduction that specifies the context and motivation of the submission.
  • A clear description of the specific contributions of your work.
  • A summary that highlights results.
  • Must use the suggested template format (found on the DVCon website).
  • Must be a minimum of 600 words - maximum of 1200 words, approximately 2 pages.
  • References, if appropriate.

   Please note: Consistent with the requirements for other DVCon presentations, your presentation may contain your company logo only on the title slide.

Conference Schedule

  • Monday, February 26: Accellera Day Tutorials, Exhibits
  • Tuesday, February 27: Technical Sessions, Exhibits, Poster Session
  • Wednesday, February 28: Technical Sessions, Exhibits
  • Thursday, March 1: Tutorials and Short Workshops

Important Deadlines

  •  July 13: Submission Site open
  • August 18: Abstract Deadline- EXTENDED!
  • October 18: Official Accept/Reject Notification sent to all authors
  • October 25: Speaker Confirmation Forms Due
  • Accepted authors will be invited and agree to do the following:
    • Submit a draft paper between October 18 and November 2 for review
    • Review and incorporate feedback from TPC, to be provided by November 30
    • Submit a final paper and copyright form by December 11
  •  All accepted authors agree to present an oral or poster presentation at the conference on either February 27 or February 28
  • Submit draft presentation slides and Speaker Bio by January 9 for review
  • Final slides are due February 13

General Chair Dennis Brophy, Mentor, A Seimens Business

dennis_brophy@mentor.com

Program Chair Tom Fitzpatrick, Mentor, A Seimens Business tom_fitzpatrick@mentor.com

Feel free to contact us for questions on the submission process at jackie@mpassociates.com or visit DVCon.org