View Call For Panels PDF

 

DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such as C and C++, PERL, Tcl and Python. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP based SoC design methods, reference flows and AMS design.

Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development, and application of Electronic Design Automation (EDA) tools. Presentations are highly technical in nature, and reflect real life experiences in using these languages and tools.

PANEL PROPOSAL

Proposals: Submit online at DVCon.org

DVCon is planning to host two highly focused panel discussions. DVCon is looking for panels that are lively, controversial, and provoke discussion on a specific topic of interest to the community. Panel sessions should not consist of paper presentations, but should have plenty of discussion engaging the audience. Panels are scheduled for 1 hour on Wednesday, February 28. Please make sure that moderator and panelists are available on Wednesday, February 28.

DVCon will attempt to work with the original organizer in refining the panel, but if this is not successful, another organizer may be appointed. If multiple panel suggestions are submitted with similar topics, the committee may choose to accept one over the others, to merge the proposed panels, or to reject all of them.

TOPIC SUGGESTIONS

We invite you to contribute your knowledge and experience within the hardware design and verification, advanced tools, and new methodologies areas, and to participate in the valuable exchange of ideas.

  • Experiences using design and/or verification IP for System-on-Chip development
  • Design and verification sign-off and closure
  • Dealing with the technical and logistical challenges of multi-site projects

  • Experiences deploying a verification methodology library, especially deployment of UVM

  • Designing and/or verifying complex ASICs and FPGAs using multiple HDLs and/or HVLs in a design cycle 

CONFERENCE SCHEDULE

  • Monday, February 26: Accellera Day Tutorials, Exhibits
  • Tuesday, February 27: Technical Sessions, Keynote Speaker, Exhibits
  • Wednesday, February 28: Technical Sessions, Panel Discussions, Exhibits
  • Thursday, March 1: Tutorials and Short Workshops

PANEL SCHEDULE

  • October 6, 2017: Proposal Deadline - EXTENDED!
  • November 2, 2017: Accept/Reject Notification
  • November 13, 2017: Final panel title, abstract, and panelist names due for website

PROPOSAL SUBMISSION

Proposals should be 2-3 pages in length and should contain:

  • The topic, if possible formulated as a provocative question
  • The issue to be discussed, including a short listing of pro and con arguments
  • Short biographies of the moderator and prospective panelists
  • Any special requirements

General Chair Dennis Brophy, Mentor, A Seimens Business dennis_brophy@mentor.com
Panel Chair Vanessa Cooper, Verilab, Inc. vanessa.cooper@verilab.com
Accellera Representative/Finance Chair Lynn Bannister, Accellera Systems Initiative lynn@accellera.org

SPONSORED BY: Accellera Systems Initiative is an industry consortium with a mission to provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process. Accellera.org

DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such as C and C++, PERL, Tcl and Python. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP based SoC design methods, reference flows and AMS design.
 
Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development, and application of Electronic Design Automation (EDA) tools. Presentations are highly technical in nature, and reflect real life experiences in using these languages and tools.
 

PANEL PROPOSAL
 
Proposals:
DVCon is planning to host two highly focused panel discussions. DVCon is looking for panels that are lively, controversial, and provoke discussion on a specific topic of interest to the community. Panel sessions should not consist of paper presentations, but should have plenty of discussion engaging the audience.  Panels are scheduled for 1 hour on Wednesday, March 4.  DVCon will select which day the panel will be presented.  Please make sure that moderator and panelists are available on Wednesday, March 4.
 
DVCon will attempt to work with the original organizer in refining the panel, but if this is not successful, another organizer may be appointed. If multiple panel suggestions are submitted with similar topics, the committee may choose to accept one over the others, to merge the proposed panels, or to reject all of them.
 
TOPIC SUGGESTIONS
 
We encourage you to contribute your experiences with hardware design and verification languages, advanced tools and methodologies, and to participate in the valuable exchange of ideas.
  • Experiences using design and/or verification IP for System-on-Chip development
  • Design and verification sign-off and closure
  • Dealing with the technical and logistical challenges of multi-site projects
  • Experiences deploying a verification methodology library, especially deployment of UVM
  • Designing and/or verifying complex ASICs and FPGAs using multiple HDLs and/or HVLs in a design cycle

 

CONFERENCE SCHEDULE
 
Monday, March 2 Tuesday, March 3
Wednesday, March 4
Thursday, March 5

•Tutorials
•Exhibits

•Technical Sessions
•Keynote Speaker
•Exhibits

•Technical Sessions
•Panel Discussions
•Exhibits

•Tutorials

 

PROPOSAL SUBMISSION
Proposals should be 2-3 pages in length and should contain:
  • The topic, if possible formulated as a provocative question
  • The issues to be discussed, including a short listing of pro and con arguments
  • Short biographies of the moderator and prospective panelists
  • Any special requirements

AUTHOR'S SCHEDULE
  • August 18, 2014: Submission site opens
  • October 2, 2014: Proposal Deadline
  • October 24, 2014: Accept / Reject notification
  • November 11, 2014: Final panel title, abstract and panelists names due for website

CONFERENCE SPONOSRED BY:
Accellera Systems Initiative is an industry consortium with a mission to provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process. www.accellera.org