Call for Panels - paragraph 2
DVCon is planning to host two highly focused panel discussions. DVCon is looking for panels that are lively, controversial, and provoke discussion on a specific topic of interest to the community. Panel sessions should not consist of paper presentations, but should have plenty of discussion engaging the audience. Panels are scheduled for 1 hour on Wednesday, March 4. DVCon will select which day the panel will be presented. Please make sure that moderator and panelists are available on Wednesday, March 4.
DVCon will attempt to work with the original organizer in refining the panel, but if this is not successful, another organizer may be appointed. If multiple panel suggestions are submitted with similar topics, the committee may choose to accept one over the others, to merge the proposed panels, or to reject all of them.
We encourage you to contribute your experiences with hardware design and verification languages, advanced tools and methodologies, and to participate in the valuable exchange of ideas.
- Experiences using design and/or verification IP for System-on-Chip development
- Design and verification sign-off and closure
- Dealing with the technical and logistical challenges of multi-site projects
- Experiences deploying a verification methodology library, especially deployment of UVM
- Designing and/or verifying complex ASICs and FPGAs using multiple HDLs and/or HVLs in a design cycle