Call for Short Workshops

 View Call For Short Workshops PDF


DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such as C, C++, PERL, Tcl, and Python. Tools and methodologies include the use of testbench automation, portable stimulus, hardware-assisted verification, hardware/software co-verification, assertion-based  and  formal verification, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP based SoC design methods, reference flows and AMS design.

DVCon is introducing short workshops to encourage greater sponsorship participation from companies and exhibitors, especially smaller organizations at an affordable level.

DVCon is looking for short workshop topics that are current, have a high-level of interest and offer strong continuing educational content. 

Short Workshop sponsors reach a captive audience during the 90-minute educational sessions and have the opportunity to follow-up with attendees during breaks, at the exhibits, and following the event.

DVCon is a highly-targeted venue for engineers addressing major design and verification issues. Submit proposals by September 29, 2017


Sponsorship Includes:

  • A 90 minute Short Workshop presentation on Thursday
  • Copy of the Short Workshop attendee list
  • Short Workshop content will be publicized via monthly newsletters, DVCon website, Conference Program and in the Opening Session presentation slides
  • One dedicated email distribution to the DVCon mail list
  • Other promotion items like banners, flyers, gift items, etc can be distributed during the Short Workshop
  • 1 complimentary one-day conference registration for the Short Workshop


  • DVCon short workshops are open to all attendees and are included in the full conference registration. Please include in the proposal the name of the companies that will be sponsoring the short workshop.
  • Attendee expectations are high regarding currency of topic, depth of engineering content and breadth of real-life examples
  • The Tutorial Chair will review final presentation materials to ensure high quality educational content
  • Include suggested presenters names, affiliations and biographies.
  • Your proposal should be a short abstract of the short workshop, two to five paragraphs, 1,000 words maximum
  • Presentation slides need to be supplied in an electronic format in advance of the conference. Presentation slides will be distributed to the attendees in electronic format. Hard copies will not be provided
  • Please indicate if this short workshop is a “hands-on” session or lecture format
  • Any necessary additional hardware that you may require must be provided by the short workshop organizers


  • SystemVerilog for Verification and/or Design
  • SystemC /C/C++ Design and/or Verification of systems.
  • SoC and Software-driven Verification
  • Assertion-based Verification. SystemVerilog Assertions, PSL, etc.
  • Coverage-driven Verification
  • High-level Synthesis
  • Low-power Design and Verification techniques
  • Secure/Encrypted IP-based SoC design methods
  • Debug for design and verification
  • Mixed-signal modeling and verification
  • Transaction Level Modeling (TLM), ESL Design, and IP integration (IP-XACT)
  • Functional Safety
  • Security
  • Embedded software verification
  • Hardware/Software Co-development
  • Verification Productivity Methods
  • Formal Methodology and Static Analysis
  • Emulation
  • Post SI Debug
  • FPGA Prototyping
  • Moving from proprietary solutions to standards-based design and verification
  • Portable Stimulus 
  • Application based design verification challenges, techniques


October 6, 2017 - Short Workshop Submission Due - EXTENDED!

November 2, 2017  -  Accept/Reject Notification

November 20, 2017  - All Short Workshop content due for Conference Program and website: title, abstract, speaker names, affiliations and biographies                               

January 18, 2018Draft Presentation slides due to DVCon Tutorial Chair

February 1, 2018  - Presentation feedback due to presenters on slides

February 13, 2018Final slides due for final production for attendee distribution


Monday, February 26

  • Accellera Day
  • Exhibits

Tuesday, February 27

  • Technical Sessions
  • Keynote Speaker
  • Exhibits

Wednesday, February 28

  • Technical Sessions
  • Panel Sessions
  • Exhibits

Thursday, March 1

  • Tutorials
  • Short Workshops

General Chair Dennis Brophy, Mentor , A Seimens Business
Tutorial/ Short Workshop Chair Aparna Dey, Cadence Design Systems, Inc.

SPONSORED BY: Accellera Systems Initiative is an industry consortium with a mission to provide design and verification standards required by systems, semiconductor, IP, and design tool companies to enhance a front-end design automation process.