Call for Tutorials - paragraph 1

DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL, SystemC and e, as well as general purpose languages such as C and C++, PERL, Tcl and Python. Tools and methodologies include the use of testbench automation, hardware-assisted verification, hardware/software co-verification, assertion-based and formal verification, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP based SoC design methods, reference flows and AMS design.
DVCon is looking for tutorial topics that are current, have a high-level of interest and offer strong continuing educational content.  

Over 300 qualified engineers attended the sponsored tutorials during DVCon 2014. Tutorial sponsors reached a captive audience during the halfday educational sessions and had the opportunity to follow-up with them during breaks, at the exhibits, and following the event.

DVCon is a highly targeted venue for engineers addressing major design and verification issues. You can position your company at the forefront of these discussions by sponsoring at either the Gold or Silver level. Submit proposals by October 3, 2014.