Committee Members on Why You Should Attend DVCon 2016
We had a number of excellent panel submissions to consider this year, and selected two that I think are of particular importance and address issues our audience is concerned with right now. Both panels will be held on Wednesday, March 2.
The first panel, “Redefining ESL” will be moderated by Brian Bailey. They will attempt to define ESL verification, from tools to flows. As they discuss, “How or when can all the disparate pieces be brought together, or is that even necessary?” there will be plenty of angles to consider.
The second panel, “Emulation + Static Verification Will Replace Simulation” will be moderated by Jim Hogan of Vista Ventures. The panel will discuss where it sees the verification paradigm of the future and where it leaves RTL simulation. It promises to be a lively discussion!
Bringing together two distinct groups of experts, I think attendees will be pleased by the different discussions and varying points of view offered by both of panels. We look forward to seeing you at DVCon U.S.!
Attendees have come to expect an in-depth, very comprehensive technical program from DVCon U.S. and this year will not disappoint.
Technical Program Standouts:
First, we have added some new sessions to the program this year such as a Design for Testing, highlighting the trend of many devices moving below 40nm geometries with requirements of lower power and area. Second, and for similar reasons, mixed-signal and low power continue their popularity in the program. Third, the industry is indeed recognizing the need to scale up both verification and design, and we have a new session dedicated to emulation. And finally, we have our ever popular sessions on UVM, advanced design and modeling approaches, improving verification processes and management, and formal methods.
What can attendees take away from DVCon U.S. this year?
A hallmark of DVCon, attendees can learn what their peers and industry leaders are working on, and how the new trends and emerging methods apply to real projects, similar to theirs. They should definitely take advantage of the one-one interactions with the poster presentations; these are exceptional and have been peer-reviewed with the same expectation for technical excellence as the oral presentations.
Ambar’s advice for attendees:
Find what your peers are working on and interact with the thought leaders in our industry. Learn where the trends are and become a thought leader yourself. Enjoy DVCon U.S. 2016!
DVCon has over the years become the top conference among the list of technical events in the field of Electronics Design and Verification. Most of the other conferences are either research & academic centric and/or full-fledged marketing extravaganza. Neither of the two is interesting for working professionals who are some of the highly paid, top notch brains in the field of engineering. The highly technical content of DVCon could well be the primary reason why you should be looking to attend it in 2016. As a member of Technical Program Committee (TPC) I have been very happy with the high quality of submissions we received this year, making our job as reviewer quite difficult. As a general guideline we kept the choice of papers wide – to cover as many attendees possible – and quite deep – in line with the growing maturity of UVM in this domain. So the attendees will find it a compelling agenda to look forward to at this year’s event. The other significant part of DVCon is the exhibit floor in which attendees get to see a preview of “What is new from the EDA vendors” and I personally have heard several engineers saying this is very useful as a refresh every year as they are mostly neck deep at work, sometimes ignoring the latest developments in the field. So please do sign-up for this event!