February 29 - March 3, 2016

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

TUESDAY March 04, 9:00am - 10:30am | Oak Ballroom

SESSION 1
Advanced Design and Verification
Event Type: REGULAR SESSION
Chair:
Charles Dawson - Cadence Design Systems, Inc.

1.1Advancing System-Level Verification Using UVM in SystemC
 Speaker: Martin Barnasconi - NXP Semiconductors
 Authors: Martin Barnasconi - NXP Semiconductors
François Pêcheux - Univ. Pierre et Marie Curie
Thilo Vörtler - Fraunhofer IIS
1.2Can My Synthesis Compiler Do That? What ASIC and FPGA Synthesis Compilers Support in the SystemVerilog-2012 Standard
 Speaker: Stuart Sutherland - Sutherland HDL, Inc.
 Authors: Stuart Sutherland - Sutherland HDL, Inc.
Don Mills - Microchip Technology, Inc.
1.3Using SystemVerilog Interfaces and Structs for RTL Design
 Speakers: Tom Symons - Oracle Corporation
Nihar Shah - Oracle Corporation
 Authors: Nihar Shah - Oracle Corporation
Tom Symons - Oracle Corporation