February 25-28, 2019

DoubleTree Hotel, San Jose, CA

MP Associates, Inc.

MONDAY March 03, 9:00am - 12:00pm | Pine/Cedar Ballroom
EVENT TYPE: TUTORIAL

SESSION 1T
UVM – What’s Now and What’s Next

Speakers:
Thomas Alsop - Intel Corp.
John Aynsley - Doulos
Shawn Honess - Synopsys, Inc.
Tom Fitzpatrick - Mentor, A Siemens Business
Uwe Simm - Cadence Design Systems, Inc.
Organizers:
Tom Alsop - Intel Corp.
Yatin Trivedi - Synopsys, Inc.
Adam Sherer - Cadence Design Systems, Inc.
The Universal Verification Methodology (UVM) has experienced great adoption and growth throughout the industry since its initial release as an Accellera standard 3 years ago. Verification engineers, EDA suppliers, service providers, and others throughout the electronics industry are actively creating verification environments following the UVM principles. Concepts like stimulus generation based on sequences, test execution using phases, communication based on transaction-level modeling (TLM), and the introduction of a register layer, all have significantly contributed to the maturity of functional verification practices.

The presenters will share their experiences on both pragmatic topics that can be applied on UVM 1.1 and advanced topics for the next update of the standard. This tutorial will assume SystemVerilog language knowledge when discussing technical content and presenting detailed examples. Among the topics will be sequence creation, register layer use (both beginner and advanced), TLM-based communication, test execution using run-time phases, and messaging enhancements. All verification engineers – from those just starting to work with the UVM to those with years of experience – will gain new knowledge from the tutorials.